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| author | Peter Stuge <peter@stuge.se> | 2007-05-10 23:50:27 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2007-05-10 23:50:27 +0000 |
| commit | deabf510bff37c1f3a1fd3ec50b88db17d38b802 (patch) | |
| tree | 3dce82f996b72212c3143dd6f68f4d9ff93081de /src/mainboard/via/epia | |
| parent | ddf845f620eb43d9ea2e8b0b265c321c6e797e6f (diff) | |
| download | coreboot-deabf510bff37c1f3a1fd3ec50b88db17d38b802.tar.xz | |
Changes by Richard Smith and Peter Stuge from the LinuxBIOS symposium 2006.
With CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0, 1 million outb():s are used
for timer calibration, which takes about one second.
All EPIA-M boards have timer2 so we use it to boot faster.
Only some EPIA boards have the Nehemiah CPU with timer2 so we default to IO
calibration but add the TSC options so that they can be set in Config.lb.
src/mainboard/via/epia*/reset.c is dead code (entire file within #if 0) so we
set HAVE_HARD_RESET=0 for both boards.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2659 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/via/epia')
| -rw-r--r-- | src/mainboard/via/epia/Options.lb | 7 | ||||
| -rw-r--r-- | src/mainboard/via/epia/reset.c | 43 |
2 files changed, 6 insertions, 44 deletions
diff --git a/src/mainboard/via/epia/Options.lb b/src/mainboard/via/epia/Options.lb index 9377b63dbd..c6be330495 100644 --- a/src/mainboard/via/epia/Options.lb +++ b/src/mainboard/via/epia/Options.lb @@ -11,6 +11,8 @@ uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET uses CONFIG_UDELAY_IO +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses HAVE_OPTION_TABLE uses USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD @@ -81,12 +83,15 @@ default HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from linuxBIOS ## -default HAVE_HARD_RESET=1 +default HAVE_HARD_RESET=0 ## ## use io based udelay function +## disable IO and enable TSC on Nehemiah boards ## default CONFIG_UDELAY_IO=1 +default CONFIG_UDELAY_TSC=0 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0 ## ## Build code to export a programmable irq routing table diff --git a/src/mainboard/via/epia/reset.c b/src/mainboard/via/epia/reset.c deleted file mode 100644 index 5796e17dc8..0000000000 --- a/src/mainboard/via/epia/reset.c +++ /dev/null @@ -1,43 +0,0 @@ -#if 0 -//#include "arch/romcc_io.h" -#include <arch/io.h> - -typedef unsigned device_t; - -#define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFF) << 16) | \ - (((DEV) & 0x1f) << 11) | \ - (((FN) & 0x7) << 8)) - -static void pci_write_config8(device_t dev, unsigned where, unsigned char value) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outb(value, 0xCFC + (addr & 3)); -} - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -static unsigned pci_read_config32(device_t dev, unsigned where) -{ - unsigned addr; - addr = dev | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} - -#include "../../../northbridge/amd/amdk8/reset_test.c" - -void hard_reset(void) -{ - set_bios_reset(); - pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1); -} -#endif |