diff options
author | Uwe Hermann <uwe@hermann-uwe.de> | 2008-10-12 11:58:26 +0000 |
---|---|---|
committer | Uwe Hermann <uwe@hermann-uwe.de> | 2008-10-12 11:58:26 +0000 |
commit | 2e5a9d952f3f3d23cf57a08abeffe3dee3444950 (patch) | |
tree | 45228e6b73c3c8299d2638b86c2ac4cbe78c790f /src/mainboard/via/pc2500e/Options.lb | |
parent | 3be4bc88fabf1a19cec38e5dbea515f1ddeb4be9 (diff) | |
download | coreboot-2e5a9d952f3f3d23cf57a08abeffe3dee3444950.tar.xz |
Add support for the VIA pc2500e mainboard (CN700 + VT8237R).
Works good enough to boot to a Linux console.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3650 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/via/pc2500e/Options.lb')
-rw-r--r-- | src/mainboard/via/pc2500e/Options.lb | 114 |
1 files changed, 114 insertions, 0 deletions
diff --git a/src/mainboard/via/pc2500e/Options.lb b/src/mainboard/via/pc2500e/Options.lb new file mode 100644 index 0000000000..fa2b02b2bb --- /dev/null +++ b/src/mainboard/via/pc2500e/Options.lb @@ -0,0 +1,114 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID +uses COREBOOT_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESSED_PAYLOAD_NRV2B +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses HAVE_MP_TABLE +uses HAVE_ACPI_TABLES +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses CONFIG_PCI_ROM_RUN +uses CONFIG_CONSOLE_VGA +uses CONFIG_MAX_PCI_BUSES +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_CHIP_NAME +uses CONFIG_VIDEO_MB +uses CONFIG_IOAPIC + +default ROM_SIZE = 512 * 1024 +default ROM_IMAGE_SIZE = 64 * 1024 +default FALLBACK_SIZE = ROM_SIZE +default CONFIG_IOAPIC = 0 +default CONFIG_VIDEO_MB = 32 +default CONFIG_CONSOLE_SERIAL8250 = 1 +default CONFIG_PCI_ROM_RUN = 0 +default CONFIG_CONSOLE_VGA = 0 +default CONFIG_CHIP_NAME = 1 +default HAVE_FALLBACK_BOOT = 1 +default HAVE_MP_TABLE = 0 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 +default HAVE_HARD_RESET = 0 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 10 +default HAVE_ACPI_TABLES = 0 +default HAVE_OPTION_TABLE = 1 +default USE_FALLBACK_IMAGE = 1 +default MAINBOARD_VENDOR = "VIA" +default MAINBOARD_PART_NUMBER = "pc2500e" +default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019 +default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0xaa51 +default STACK_SIZE = 8 * 1024 +default HEAP_SIZE = 16 * 1024 +# default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 1 +default _RAMBASE = 0x00004000 +default CONFIG_ROM_PAYLOAD = 1 +default CROSS_COMPILE = "" +default CC = "$(CROSS_COMPILE)gcc -m32 -fno-stack-protector" +default HOSTCC = "gcc" +default CONFIG_MAX_PCI_BUSES = 3 +default CONFIG_CONSOLE_SERIAL8250 = 1 +default TTYS0_BAUD = 115200 +default TTYS0_BASE = 0x3f8 +default TTYS0_LCS = 0x3 +default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default DEFAULT_CONSOLE_LOGLEVEL = 9 + +end + |