geeesh! And this really compiles and even runs?

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5431 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 57 insertions, 58 deletions

diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c
index 6f8a1c09da..ab148e478d 100644
--- a/src/mainboard/via/epia-m700/romstage.c
+++ b/src/mainboard/via/epia-m700/romstage.c
@@ -58,7 +58,7 @@
  * This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list:
  * http://www.coreboot.org/pipermail/coreboot/2008-January/028787.html.
  */
-int acpi_is_wakeup_early_via_vx800(void)
+static int acpi_is_wakeup_early_via_vx800(void)
 {
 	device_t dev;
 	u16 tmp, result;
@@ -94,8 +94,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 static void enable_mainboard_devices(void)
 {
 	device_t dev;
-	uint16_t values;
-
 #if 0
 	/*
 	 * Add and close this switch, since some line cause error, some
@@ -145,6 +143,8 @@ static void enable_mainboard_devices(void)
 #if 0
 	dev = 0;
 	dev = pci_locate_device(PCI_ID(0x1106, PCI_DEVICE_ID_VIA_VX855_IDE), 0);
+
+	uint16_t values;
 	values = pci_read_config16(dev, 0xBA);
 	values &= ~0xffff;
 	values |= 0x5324;
@@ -202,68 +202,68 @@ static void enable_shadow_ram(void)
  */
 static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = {
 	/* VT3409 no PCI-E */
-	0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E,	// Set Exxxxxxx as pcie mmio config range
-	0x00, 0xFF, NB_APIC_REG(0x60), 0xF4, 0x0B,	// Support extended cfg address of pcie
-	// 0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02, // APIC Interrupt((BT_INTR)) Control
+	{ 0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E },	// Set Exxxxxxx as pcie mmio config range
+	{ 0x00, 0xFF, NB_APIC_REG(0x60), 0xF4, 0x0B },	// Support extended cfg address of pcie
+	// { 0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02 }, // APIC Interrupt((BT_INTR)) Control
 	// Set ROMSIP value by software
 
 	/*
-	0x00, 0xFF, NB_HOST_REG(0x70), 0x77, 0x33, // 2x Host Adr Strobe/Pad Pullup Driving = 3
-	0x00, 0xFF, NB_HOST_REG(0x71), 0x77, 0x33, // 2x Host Adr Strobe/Pad Pulldown Driving = 3
-	0x00, 0xFF, NB_HOST_REG(0x72), 0x77, 0x33, // 4x Host Dat Strobe/Pad Pullup Driving = 3
-	0x00, 0xFF, NB_HOST_REG(0x73), 0x77, 0x33, // 4x Host Dat Strobe/Pad Pulldown Driving = 3
-	0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0x21, // Memory I/F timing ctrl
-	0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0xE1, // Memory I/F timing ctrl
-	0x00, 0xFF, NB_HOST_REG(0x75), 0xFF, 0x18, // AGTL+ I/O Circuit
-	0x00, 0xFF, NB_HOST_REG(0x76), 0xFB, 0x0C, // AGTL+ Compensation Status
-	0x00, 0xFF, NB_HOST_REG(0x78), 0xFF, 0x33, // 2X AGTL+ Auto Compensation Offset
-	0x00, 0xFF, NB_HOST_REG(0x79), 0xFF, 0x33, // 4X AGTL+ Auto Compensation Offset
-	0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x72, // AGTL Compensation Status
-	0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x77, // AGTL Compensation Status
-	0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x44, // Input Host Address / Host Strobe Delay Control for HA Group
-	0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x22, // Input Host Address / Host Strobe Delay Control for HA Group
-	0x00, 0xFF, NB_HOST_REG(0x7C), 0xFF, 0x00, // Output Delay Control of PAD for HA Group
-	0x00, 0xFF, NB_HOST_REG(0x7D), 0xFF, 0xAA, // Host Address / Address Clock Output Delay Control (Only for P4 Bus)
-	0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x10, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
-	0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x40, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
-	0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x10, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
-	0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x40, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
-	0x00, 0xFF, NB_HOST_REG(0x80), 0x3F, 0x44, // Host Data Receiving Strobe Delay Ctrl 1
-	0x00, 0xFF, NB_HOST_REG(0x81), 0xFF, 0x44, // Host Data Receiving Strobe Delay Ctrl 2
-	0x00, 0xFF, NB_HOST_REG(0x82), 0xFF, 0x00, // Output Delay of PAD for HDSTB
-	0x00, 0xFF, NB_HOST_REG(0x83), 0xFF, 0x00, // Output Delay of PAD for HD
-	0x00, 0xFF, NB_HOST_REG(0x84), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 0)
-	0x00, 0xFF, NB_HOST_REG(0x85), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 1)
-	0x00, 0xFF, NB_HOST_REG(0x86), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 2)
-	0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 3)
+	{ 0x00, 0xFF, NB_HOST_REG(0x70), 0x77, 0x33 }, // 2x Host Adr Strobe/Pad Pullup Driving = 3
+	{ 0x00, 0xFF, NB_HOST_REG(0x71), 0x77, 0x33 }, // 2x Host Adr Strobe/Pad Pulldown Driving = 3
+	{ 0x00, 0xFF, NB_HOST_REG(0x72), 0x77, 0x33 }, // 4x Host Dat Strobe/Pad Pullup Driving = 3
+	{ 0x00, 0xFF, NB_HOST_REG(0x73), 0x77, 0x33 }, // 4x Host Dat Strobe/Pad Pulldown Driving = 3
+	{ 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0x21 }, // Memory I/F timing ctrl
+	{ 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0xE1 }, // Memory I/F timing ctrl
+	{ 0x00, 0xFF, NB_HOST_REG(0x75), 0xFF, 0x18 }, // AGTL+ I/O Circuit
+	{ 0x00, 0xFF, NB_HOST_REG(0x76), 0xFB, 0x0C }, // AGTL+ Compensation Status
+	{ 0x00, 0xFF, NB_HOST_REG(0x78), 0xFF, 0x33 }, // 2X AGTL+ Auto Compensation Offset
+	{ 0x00, 0xFF, NB_HOST_REG(0x79), 0xFF, 0x33 }, // 4X AGTL+ Auto Compensation Offset
+	{ 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x72 }, // AGTL Compensation Status
+	{ 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x77 }, // AGTL Compensation Status
+	{ 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x44 }, // Input Host Address / Host Strobe Delay Control for HA Group
+	{ 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x22 }, // Input Host Address / Host Strobe Delay Control for HA Group
+	{ 0x00, 0xFF, NB_HOST_REG(0x7C), 0xFF, 0x00 }, // Output Delay Control of PAD for HA Group
+	{ 0x00, 0xFF, NB_HOST_REG(0x7D), 0xFF, 0xAA }, // Host Address / Address Clock Output Delay Control (Only for P4 Bus)
+	{ 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x10 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
+	{ 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x40 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
+	{ 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x10 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
+	{ 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x40 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
+	{ 0x00, 0xFF, NB_HOST_REG(0x80), 0x3F, 0x44 }, // Host Data Receiving Strobe Delay Ctrl 1
+	{ 0x00, 0xFF, NB_HOST_REG(0x81), 0xFF, 0x44 }, // Host Data Receiving Strobe Delay Ctrl 2
+	{ 0x00, 0xFF, NB_HOST_REG(0x82), 0xFF, 0x00 }, // Output Delay of PAD for HDSTB
+	{ 0x00, 0xFF, NB_HOST_REG(0x83), 0xFF, 0x00 }, // Output Delay of PAD for HD
+	{ 0x00, 0xFF, NB_HOST_REG(0x84), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 0)
+	{ 0x00, 0xFF, NB_HOST_REG(0x85), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 1)
+	{ 0x00, 0xFF, NB_HOST_REG(0x86), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 2)
+	{ 0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 3)
 	*/
 
 	// CPU Host Bus Control
-	0x00, 0xFF, NB_HOST_REG(0x50), 0x1F, 0x08,	// Request phase ctrl: Dynamic Defer Snoop Stall Count = 8
-	// 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F,	// CPU I/F Ctrl-1: Disable Fast DRDY and RAW
-	0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7C,	// CPU I/F Ctrl-1: Disable Fast DRDY and RAW
-	0x00, 0xFF, NB_HOST_REG(0x52), 0xCB, 0xCB,	// CPU I/F Ctrl-2: Enable all for performance
-	// 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88,	// Arbitration: Host/Master Occupancy timer = 8*4 HCLK
-	0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x44,	// Arbitration: Host/Master Occupancy timer = 4*4 HCLK
-	0x00, 0xFF, NB_HOST_REG(0x54), 0x1E, 0x1C,	// Misc Ctrl: Enable 8QW burst Mem Access
-	// 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06,	// Miscellaneous Control 2
-	0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x04,	// Miscellaneous Control 2
-	0x00, 0xFF, NB_HOST_REG(0x56), 0xF7, 0x63,	// Write Policy 1
-	// 0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01,	// CPU Miscellaneous Control 1, enable Lowest-Priority IPL
-	// 0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00,	// CPU Miscellaneous Control 2
-	0x00, 0xFF, NB_HOST_REG(0x5D), 0xFF, 0xA2,	// Write Policy
-	0x00, 0xFF, NB_HOST_REG(0x5E), 0xFF, 0x88,	// Bandwidth Timer
-	0x00, 0xFF, NB_HOST_REG(0x5F), 0x46, 0x46,	// CPU Misc Ctrl
-	// 0x00, 0xFF, NB_HOST_REG(0x90), 0xFF, 0x0B,	// CPU Miscellaneous Control 3
-	// 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B,	// CPU Miscellaneous Control 2
-	0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0A,	// CPU Miscellaneous Control 2
-	0x00, 0xFF, NB_HOST_REG(0x98), 0xC1, 0x41,	// CPU Miscellaneous Control 3
-	0x00, 0xFF, NB_HOST_REG(0x99), 0x0E, 0x06,	// CPU Miscellaneous Control 4
+	{ 0x00, 0xFF, NB_HOST_REG(0x50), 0x1F, 0x08 },	// Request phase ctrl: Dynamic Defer Snoop Stall Count = 8
+	// { 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F },	// CPU I/F Ctrl-1: Disable Fast DRDY and RAW
+	{ 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7C },	// CPU I/F Ctrl-1: Disable Fast DRDY and RAW
+	{ 0x00, 0xFF, NB_HOST_REG(0x52), 0xCB, 0xCB },	// CPU I/F Ctrl-2: Enable all for performance
+	// { 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88 },	// Arbitration: Host/Master Occupancy timer = 8*4 HCLK
+	{ 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x44 },	// Arbitration: Host/Master Occupancy timer = 4*4 HCLK
+	{ 0x00, 0xFF, NB_HOST_REG(0x54), 0x1E, 0x1C },	// Misc Ctrl: Enable 8QW burst Mem Access
+	// { 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06 },	// Miscellaneous Control 2
+	{ 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x04 },	// Miscellaneous Control 2
+	{ 0x00, 0xFF, NB_HOST_REG(0x56), 0xF7, 0x63 },	// Write Policy 1
+	// { 0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01 },	// CPU Miscellaneous Control 1, enable Lowest-Priority IPL
+	// { 0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00 },	// CPU Miscellaneous Control 2
+	{ 0x00, 0xFF, NB_HOST_REG(0x5D), 0xFF, 0xA2 },	// Write Policy
+	{ 0x00, 0xFF, NB_HOST_REG(0x5E), 0xFF, 0x88 },	// Bandwidth Timer
+	{ 0x00, 0xFF, NB_HOST_REG(0x5F), 0x46, 0x46 },	// CPU Misc Ctrl
+	// { 0x00, 0xFF, NB_HOST_REG(0x90), 0xFF, 0x0B },	// CPU Miscellaneous Control 3
+	// { 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B },	// CPU Miscellaneous Control 2
+	{ 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0A },	// CPU Miscellaneous Control 2
+	{ 0x00, 0xFF, NB_HOST_REG(0x98), 0xC1, 0x41 },	// CPU Miscellaneous Control 3
+	{ 0x00, 0xFF, NB_HOST_REG(0x99), 0x0E, 0x06 },	// CPU Miscellaneous Control 4
 
 	// Set APIC and SMRAM
-	0x00, 0xFF, NB_HOST_REG(0x97), 0xFF, 0x00,	// APIC Related Control
-	0x00, 0xFF, NB_DRAMC_REG(0x86), 0xD6, 0x29,	// SMM and APIC Decoding: enable APIC, MSI and SMRAM A-Seg
-	0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00	// End of the table
+	{ 0x00, 0xFF, NB_HOST_REG(0x97), 0xFF, 0x00 },	// APIC Related Control
+	{ 0x00, 0xFF, NB_DRAMC_REG(0x86), 0xD6, 0x29 },	// SMM and APIC Decoding: enable APIC, MSI and SMRAM A-Seg
+	{ 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }	// End of the table
 };
 
 #define USE_VCP     1		/* 0 means "use DVP". */
@@ -383,7 +383,6 @@ void EmbedComInit(void)
 /* cache_as_ram.inc jumps to here. */
 void main(unsigned long bist)
 {
-	unsigned cpu_reset = 0;
 	u16 boot_mode;
 	u8 rambits, Data8, Data;
 	device_t device;