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authorRichard Smith <smithbone@gmail.com>2006-04-23 23:12:21 +0000
committerRichard Smith <smithbone@gmail.com>2006-04-23 23:12:21 +0000
commit2a7352cb9dd7211c9a7edbef5145dd59df264644 (patch)
treefd50995bb28ef91e18abfb3fa833f1eb2e07c1f8 /src/mainboard/via
parent2f1980026865af7b11f27257c36b61d897932186 (diff)
downloadcoreboot-2a7352cb9dd7211c9a7edbef5145dd59df264644.tar.xz
Adds a CONFIG_MAX_PCI_BUSES to pci_locate_device()
Default is 255. This allows mainboard configs for working across various groups of boards that differ a device that may not loaded. If you search for a device that is not loaded and max buses is 255 then there can be up to a 8 second delay to search the entire PCI space. Board configs that know thier max bus can limit this search space. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/via')
-rw-r--r--src/mainboard/via/epia-m/Options.lb10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/via/epia-m/Options.lb b/src/mainboard/via/epia-m/Options.lb
index 6c3193e78d..735d4421a0 100644
--- a/src/mainboard/via/epia-m/Options.lb
+++ b/src/mainboard/via/epia-m/Options.lb
@@ -38,6 +38,7 @@ uses CONFIG_CONSOLE_SERIAL8250
uses CONFIG_UDELAY_TSC
uses CONFIG_PCI_ROM_RUN
uses CONFIG_CONSOLE_VGA
+uses CONFIG_MAX_PCI_BUSES
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
@@ -121,5 +122,14 @@ default CROSS_COMPILE=""
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
+##
+## Set this to the max PCI bus number you
+## would ever use for PCI config IO.
+## Setting this number very high will make
+## pci_locate_device take a long time when
+## it can't find a device.
+##
+default CONFIG_MAX_PCI_BUSES = 5
+
end