diff options
author | Aaron Durbin <adurbin@chromium.org> | 2014-08-14 08:35:11 -0500 |
---|---|---|
committer | Aaron Durbin <adurbin@google.com> | 2014-08-15 03:44:46 +0200 |
commit | a0a3727dbbd7f3ae9f9021e0797ce2fc61d1b79e (patch) | |
tree | a0233b3d5b638eb05bf5a4d57ee64e73187da677 /src/mainboard/via | |
parent | b7f1bfcf289f218f05dfb17561a5b868eea65b92 (diff) | |
download | coreboot-a0a3727dbbd7f3ae9f9021e0797ce2fc61d1b79e.tar.xz |
intel/cpu: rename car.h to romstage.h
This header has nothing to do with cache-as-ram. Therefore, 'car'
is the wrong term to use. It is about providing a prototype for
*romstage*.
Change-Id: Ibc5bc6f3c38e74d6337c12f246846853ceae4743
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6661
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/via')
-rw-r--r-- | src/mainboard/via/epia-cn/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/via/epia-m/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/via/epia-m700/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/via/epia-m850/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/via/epia-n/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/via/epia/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/via/pc2500e/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/via/vt8454c/romstage.c | 2 |
8 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index e7e65f2d44..20f99cb624 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -79,7 +79,7 @@ static const struct mem_controller ctrl = { .channel0 = { DIMM0 }, }; -#include <cpu/intel/car.h> +#include <cpu/intel/romstage.h> void main(unsigned long bist) { /* Enable multifunction for northbridge. */ diff --git a/src/mainboard/via/epia-m/romstage.c b/src/mainboard/via/epia-m/romstage.c index b3b515df2b..3f2a0c4084 100644 --- a/src/mainboard/via/epia-m/romstage.c +++ b/src/mainboard/via/epia-m/romstage.c @@ -66,7 +66,7 @@ static void enable_shadow_ram(void) pci_write_config8(dev, 0x63, shadowreg); } -#include <cpu/intel/car.h> +#include <cpu/intel/romstage.h> static void main(unsigned long bist) { device_t dev; diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index c33acbe24b..b00ece1a3a 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -373,7 +373,7 @@ static void EmbedComInit(void) #endif /* cache_as_ram.inc jumps to here. */ -#include <cpu/intel/car.h> +#include <cpu/intel/romstage.h> void main(unsigned long bist) { u16 boot_mode; diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index 969e2b6aec..7b62d86105 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -42,7 +42,7 @@ #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) /* cache_as_ram.inc jumps to here. */ -#include <cpu/intel/car.h> +#include <cpu/intel/romstage.h> void main(unsigned long bist) { u32 tolm; diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c index 5c1477d3a9..2ede8d87cb 100644 --- a/src/mainboard/via/epia-n/romstage.c +++ b/src/mainboard/via/epia-n/romstage.c @@ -101,7 +101,7 @@ static void enable_shadow_ram(void) pci_write_config8(ctrl.d0f3, 0x82, shadowreg); } -#include <cpu/intel/car.h> +#include <cpu/intel/romstage.h> static void main(unsigned long bist) { unsigned long x; diff --git a/src/mainboard/via/epia/romstage.c b/src/mainboard/via/epia/romstage.c index e839541a27..1d312d7267 100644 --- a/src/mainboard/via/epia/romstage.c +++ b/src/mainboard/via/epia/romstage.c @@ -69,7 +69,7 @@ static void enable_shadow_ram(void) pci_write_config8(dev, 0x63, shadowreg); } -#include <cpu/intel/car.h> +#include <cpu/intel/romstage.h> static void main(unsigned long bist) { if (bist == 0) diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index aa7e2de6ec..0b1aeb4761 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -55,7 +55,7 @@ static const struct mem_controller ctrl = { .channel0 = { DIMM0 }, /* TODO: CN700 currently only supports 1 DIMM. */ }; -#include <cpu/intel/car.h> +#include <cpu/intel/romstage.h> void main(unsigned long bist) { /* Enable multifunction for northbridge. */ diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index d3ad0e2964..f6d58c8e70 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -83,7 +83,7 @@ static void enable_shadow_ram(const struct mem_controller *ctrl) pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg); } -#include <cpu/intel/car.h> +#include <cpu/intel/romstage.h> void main(unsigned long bist) { /* Set statically so it should work with cx700 as well */ |