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authorStefan Reinauer <stefan.reinauer@coreboot.org>2011-04-20 20:54:07 +0000
committerStefan Reinauer <stepan@openbios.org>2011-04-20 20:54:07 +0000
commit42fa7fe28b60b448f501e99ee285a0af12c86d34 (patch)
tree247586f11a5be9dcbea2cbafaede92df058ac14b /src/mainboard/winent/pl6064
parentd8129f92c0cbd6a561195c1628ba3f9f98eccd50 (diff)
downloadcoreboot-42fa7fe28b60b448f501e99ee285a0af12c86d34.tar.xz
run uart_init() from console_init, just like the other console initialization functions.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/winent/pl6064')
-rw-r--r--src/mainboard/winent/pl6064/romstage.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c
index a3c92346d9..a8b684e5a3 100644
--- a/src/mainboard/winent/pl6064/romstage.c
+++ b/src/mainboard/winent/pl6064/romstage.c
@@ -72,7 +72,6 @@ void main(unsigned long bist)
*/
w83627hf_set_clksel_48(SERIAL_DEV);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- uart_init();
console_init();
/* Halt if there was a built in self test failure */
@@ -85,5 +84,4 @@ void main(unsigned long bist)
sdram_initialize(1, memctrl);
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
- return;
}