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| author | Patrick Georgi <patrick@georgi-clan.de> | 2012-07-13 19:06:22 +0200 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2012-07-26 21:33:31 +0200 |
| commit | 7dc2864be7fcc342bab0c167997803f5faf147a1 (patch) | |
| tree | bf94e8694da70ef352eca13a04945e0ddc7c5e70 /src/mainboard/winent/pl6064 | |
| parent | 1b3207ee617c24fd283e654359c20c88d95a69c8 (diff) | |
| download | coreboot-7dc2864be7fcc342bab0c167997803f5faf147a1.tar.xz | |
amd/lx: Move configuration from source to Kconfig
LX has two values that are usually automatically derived but can
be overridden, that were so far defined in each board's romstage.
These values, along with the toggle to enable override are now
part of LX's Kconfig. For boards that gave values but requested
autogeneration, the values are removed.
Further improvements: Figure out the various fields in PLLMSRlo
and make them sensible Kconfig options (instead of the hex value
it is now)
Change-Id: I8a17c89e4a3cb1b52aaceef645955ab7817b482d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1227
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/winent/pl6064')
| -rw-r--r-- | src/mainboard/winent/pl6064/romstage.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index 6651acd4ca..39e4ecf8b0 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -43,10 +43,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ -#define PLLMSRlo 0x02000030 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" @@ -77,7 +73,7 @@ void main(unsigned long bist) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - pll_reset(ManualConf); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); |