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authorNils Jacobs <njacobs8@hetnet.nl>2010-05-08 21:50:31 +0000
committerStefan Reinauer <stepan@openbios.org>2010-05-08 21:50:31 +0000
commitd37ce2e28eaa7607442bf3670ed2daec3724dc24 (patch)
tree94f97e85ce82d726722e8791143ba0aa0f67f99d /src/mainboard/wyse/s50/devicetree.cb
parent133887d540620d1c13cf3f3be0fdd46cd7adcff1 (diff)
downloadcoreboot-d37ce2e28eaa7607442bf3670ed2daec3724dc24.tar.xz
Add the Wyse S50 thin client to Coreboot.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5533 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/wyse/s50/devicetree.cb')
-rw-r--r--src/mainboard/wyse/s50/devicetree.cb32
1 files changed, 32 insertions, 0 deletions
diff --git a/src/mainboard/wyse/s50/devicetree.cb b/src/mainboard/wyse/s50/devicetree.cb
new file mode 100644
index 0000000000..76a8a04c6e
--- /dev/null
+++ b/src/mainboard/wyse/s50/devicetree.cb
@@ -0,0 +1,32 @@
+chip northbridge/amd/gx2
+ register "irqmap" = "0xaa5b"
+ register "setupflash" = "0"
+ device lapic_cluster 0 on
+ chip cpu/amd/model_gx2
+ device lapic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ device pci 1.0 on end
+ device pci 1.1 on end
+ chip southbridge/amd/cs5536
+ register "enable_gpio_int_route" = "0x0D0C0700"
+ register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+ register "enable_USBP4_device" = "0" #0: host, 1:device
+ register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+ register "com1_enable" = "1"
+ register "com1_address" = "0x3F8"
+ register "com1_irq" = "4"
+ register "com2_enable" = "0"
+ register "com2_address" = "0x2F8"
+ register "com2_irq" = "3"
+ device pci e.0 on end # Realtek 8139 LAN
+ device pci f.0 on end # ISA Bridge
+ device pci f.2 on end # IDE Controller
+ device pci f.3 on end # Audio
+ device pci f.4 on end # OHCI
+ device pci f.5 on end # EHCI
+ end
+ end
+end
+