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authorNils Jacobs <njacobs8@hetnet.nl>2010-11-01 15:20:27 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-11-01 15:20:27 +0000
commit76890dde1428741a7c91732b04cc3c95ada9c321 (patch)
treee57fa1bfddf42afcf6a20cd8581f84ff896080b3 /src/mainboard/wyse
parent96446239346128308a9f8500c4018aae579a876d (diff)
downloadcoreboot-76890dde1428741a7c91732b04cc3c95ada9c321.tar.xz
Change Geode GX2 to use the auto DRAM detect code from Geode LX.
Also, change the GX2 boards to use it. Add a processor speed setting function in human readable MHz and remove the useless and broken PLLMSR settings (the processor speed was hardcoded to 366MHz in pll_reset.c). Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/wyse')
-rw-r--r--src/mainboard/wyse/s50/romstage.c87
1 files changed, 8 insertions, 79 deletions
diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c
index a77760d6ef..64849be771 100644
--- a/src/mainboard/wyse/s50/romstage.c
+++ b/src/mainboard/wyse/s50/romstage.c
@@ -34,92 +34,21 @@
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/gx2/raminit.h"
-
- /* This is needed because ROMCC doesn`t now the ctz bitop */
-static inline unsigned int ctz(unsigned int n)
-{
- int zeros;
-
- n = (n ^ (n - 1)) >> 1;
- for (zeros = 0; n; zeros++)
- {
- n >>= 1;
- }
- return zeros;
-}
+#define DIMM0 0xA0
+#define DIMM1 0xA2
-static void sdram_set_spd_registers(const struct mem_controller *ctrl)
+static inline int spd_read_byte(unsigned int device, unsigned int address)
{
- /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) *
- * component Banks (byte 17) * module banks, side (byte 5) *
- * width in bits (byte 6,7)
- * = Density per side (byte 31) * number of sides (byte 5) */
- /* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */
- msr_t msr;
- unsigned char module_banks, val;
- uint16_t dimm_size;
-
- msr = rdmsr(MC_CF07_DATA);
-
- /* get module banks (sides) per dimm, SPD byte 5 */
- module_banks = spd_read_byte(0xA0, 5);
- if (module_banks < 1 || module_banks > 2)
- print_err("Module banks per dimm\n");
- module_banks >>= 1;
- msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT);
- msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT);
-
- /* get component banks per module bank, SPD byte 17 */
- val = spd_read_byte(0xA0, 17);
- if (val < 2 || val > 4)
- print_err("Component banks per module bank\n");
- val >>= 2;
- msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT);
- msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT);
-
- dimm_size = spd_read_byte(0xA0, 31);
- dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */
- dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */
- /* Module Density * Module Banks */
- dimm_size <<= (0 >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */
- if (dimm_size != 0) {
- dimm_size = ctz(dimm_size);
- }
- if (dimm_size > 7) { /* 7 is 512MB only support 512MB per DIMM */
- print_err("Only support up to 512MB \n");
- hlt();
- }
- msr.hi |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
-
- /* page size = 2^col address */
- val = spd_read_byte(0xA0, 4);
- val -= 7;
- msr.hi &= ~(0x7 << CF07_UPPER_D0_PSZ_SHIFT);
- msr.hi |= (val << CF07_UPPER_D0_PSZ_SHIFT);
-
- print_debug("computed msr.hi ");
- print_debug_hex32(msr.hi);
- print_debug("\n");
-
- msr.lo = 0x00003400;
- wrmsr(MC_CF07_DATA, msr);
-
- msr = rdmsr(MC_CF8F_DATA);
- msr.hi = 0x18000008;
- msr.lo = 0x296332a3;
- wrmsr(MC_CF8F_DATA, msr);
+ if (device != DIMM0)
+ return 0xFF; /* No DIMM1, don't even try. */
+ return smbus_read_byte(device, address);
}
+#include "northbridge/amd/gx2/raminit.h"
+#include "northbridge/amd/gx2/pll_reset.c"
#include "northbridge/amd/gx2/raminit.c"
#include "lib/generic_sdram.c"
-#include "northbridge/amd/gx2/pll_reset.c"
#include "cpu/amd/model_gx2/cpureginit.c"
#include "cpu/amd/model_gx2/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"