summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
authorVincent Palatin <vpalatin@chromium.org>2017-03-15 15:37:51 +0100
committerDuncan Laurie <dlaurie@chromium.org>2017-03-15 19:54:47 +0100
commit08824ec8d4d68ffa9edf1212e7f7e281da4d779f (patch)
tree5e3b91e1321a4a7a2456b9161e4b0b7fede8344a /src/mainboard
parent57e9e3be5fe3a68c8ccedc85e673f091aaf8ff58 (diff)
downloadcoreboot-08824ec8d4d68ffa9edf1212e7f7e281da4d779f.tar.xz
google/eve: Update MCU GPIOs configuration
Keep the BOOT0 pin triggering the MCU bootloader as an input, so the Servo debug board doesn't have to fight with the PCH to program it, the net already has an external pull-down to ensure that the MCU is in normal mode at boot. By default, do not drive the FP sensor reset from the PCH, the MCU is now managing the reset line (but the PCH still has a connection on the current boards). BRANCH=none BUG=b:36025702 TEST=manual testing, program the MCU through a Servo v2 board, and use the FP sensor through the MCU and verify it is not stuck under reset. Change-Id: I19113b5d78013d0ab6ec5a72c6f71dd4c67a88e8 Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://review.coreboot.org/18830 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/eve/gpio.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h
index deb0192111..d72b492c6b 100644
--- a/src/mainboard/google/eve/gpio.h
+++ b/src/mainboard/google/eve/gpio.h
@@ -104,9 +104,9 @@ static const struct pad_config gpio_table[] = {
/* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
/* SM1DATA */ PAD_CFG_NC(GPP_C7),
/* UART0_RXD */ PAD_CFG_GPI(GPP_C8, NONE, PLTRST), /* FP_INT */
-/* UART0_TXD */ PAD_CFG_GPO(GPP_C9, 1, DEEP), /* FP_RST_ODL */
+/* UART0_TXD */ PAD_CFG_GPI(GPP_C9, NONE, DEEP), /* FP_RST_ODL */
/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* PCH_FPS_MCU_NRST_ODL */
-/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FPS_MCU_BOOT0 */
+/* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* PCH_FPS_MCU_BOOT0 */
/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */
/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */
/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */
@@ -233,9 +233,9 @@ static const struct pad_config early_gpio_table[] = {
static const struct pad_config late_gpio_table[] = {
/* UART0_RXD */ PAD_CFG_GPI(GPP_C8, NONE, PLTRST), /* FP_INT */
-/* UART0_TXD */ PAD_CFG_GPO(GPP_C9, 1, DEEP), /* FP_RST_ODL */
+/* UART0_TXD */ PAD_CFG_GPI(GPP_C9, NONE, DEEP), /* FP_RST_ODL */
/* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* PCH_FPS_MCU_NRST_ODL */
-/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FPS_MCU_BOOT0 */
+/* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* PCH_FPS_MCU_BOOT0 */
};
#endif