summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
authorFelix Singer <felixsinger@posteo.net>2020-07-29 19:57:25 +0200
committerMichael Niewöhner <c0d3z3r0@review.coreboot.org>2020-07-29 20:45:29 +0000
commit0901d03085e091a26fdc00da09a1e8e0b05adf86 (patch)
tree8513085e64129afa84ad9a8f4c16e9e73eb92923 /src/mainboard
parent3c0486913fea834336ebd6bf98f326aa4ba6e5c8 (diff)
downloadcoreboot-0901d03085e091a26fdc00da09a1e8e0b05adf86.tar.xz
soc/intel/skylake: Enable SATA depending on devicetree configuration
Currently SATA gets enabled by the option EnableSata, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the SATA controller. I checked all corresponding mainboards if the devicetree configuration matches the EnableSata setting. Change-Id: I217dcb7178f29bbdeada54bdb774166126b47a5a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/51nb/x210/devicetree.cb1
-rw-r--r--src/mainboard/asrock/h110m/devicetree.cb1
-rw-r--r--src/mainboard/facebook/monolith/devicetree.cb23
-rw-r--r--src/mainboard/google/eve/devicetree.cb1
-rw-r--r--src/mainboard/google/fizz/variants/baseboard/devicetree.cb1
-rw-r--r--src/mainboard/google/glados/devicetree.cb1
-rw-r--r--src/mainboard/google/poppy/variants/atlas/devicetree.cb1
-rw-r--r--src/mainboard/google/poppy/variants/baseboard/devicetree.cb1
-rw-r--r--src/mainboard/google/poppy/variants/nami/devicetree.cb1
-rw-r--r--src/mainboard/google/poppy/variants/nautilus/devicetree.cb1
-rw-r--r--src/mainboard/google/poppy/variants/nocturne/devicetree.cb1
-rw-r--r--src/mainboard/google/poppy/variants/rammus/devicetree.cb1
-rw-r--r--src/mainboard/google/poppy/variants/soraka/devicetree.cb1
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb1
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb1
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb1
-rw-r--r--src/mainboard/intel/saddlebrook/devicetree.cb1
-rw-r--r--src/mainboard/libretrend/lt1000/devicetree.cb1
-rw-r--r--src/mainboard/protectli/vault_kbl/devicetree.cb1
-rw-r--r--src/mainboard/purism/librem_skl/devicetree.cb1
-rw-r--r--src/mainboard/razer/blade_stealth_kbl/devicetree.cb1
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/devicetree.cb1
22 files changed, 11 insertions, 33 deletions
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb
index 8e775b51a3..398271ea99 100644
--- a/src/mainboard/51nb/x210/devicetree.cb
+++ b/src/mainboard/51nb/x210/devicetree.cb
@@ -37,7 +37,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
- register "EnableSata" = "1"
register "SataSalpSupport" = "1"
register "SataMode" = "0"
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb
index 977fa2982d..c185b10143 100644
--- a/src/mainboard/asrock/h110m/devicetree.cb
+++ b/src/mainboard/asrock/h110m/devicetree.cb
@@ -154,7 +154,6 @@ chip soc/intel/skylake
register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)"
# SATA
- register "EnableSata" = "1"
register "SataSalpSupport" = "1"
# SATA4 and SATA5 are located in the lower right corner of the board,
# but they are not populated. This is because the same PCB is used to
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb
index 751da3e07b..f9a2b6632d 100644
--- a/src/mainboard/facebook/monolith/devicetree.cb
+++ b/src/mainboard/facebook/monolith/devicetree.cb
@@ -49,18 +49,17 @@ chip soc/intel/skylake
register "HeciEnabled" = "0"
register "EnableLan" = "1"
- register "EnableSata" = "1"
- register "SataSalpSupport" = "1"
- register "SataPortsEnable" = "{ \
- [0] = 1, \
- [1] = 0, \
- [2] = 0, \
- [3] = 0, \
- [4] = 0, \
- [5] = 0, \
- [6] = 0, \
- [7] = 0, \
- }"
+ register "SataSalpSupport" = "1"
+ register "SataPortsEnable" = "{ \
+ [0] = 1, \
+ [1] = 0, \
+ [2] = 0, \
+ [3] = 0, \
+ [4] = 0, \
+ [5] = 0, \
+ [6] = 0, \
+ [7] = 0, \
+ }"
# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index e26128dc1e..64241f8de9 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -37,7 +37,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
- register "EnableSata" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
index d959b81157..4bd4d33430 100644
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -66,7 +66,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
- register "EnableSata" = "1"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "1"
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 84e9693ed4..739ecc6977 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -39,7 +39,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
- register "EnableSata" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index d54f7162a6..2634a57931 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -43,7 +43,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
- register "EnableSata" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index f270b19cd8..67864f4beb 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -33,7 +33,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
- register "EnableSata" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index 78c7d36c63..1bb88aba64 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -33,7 +33,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
- register "EnableSata" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "EnableAzalia" = "1"
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index 78126460b3..7b0fe60ff8 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -33,7 +33,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
- register "EnableSata" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 2eb7bd2436..3d255c1d97 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -38,7 +38,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
- register "EnableSata" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
index 531e30db41..e669fe5200 100644
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -43,7 +43,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
- register "EnableSata" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index 03f2979f0f..ec896ebbe2 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -33,7 +33,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
- register "EnableSata" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
index fa502834af..b5979fc8a8 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
@@ -84,7 +84,6 @@ chip soc/intel/skylake
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
- register "EnableSata" = "1"
register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{ \
[0] = 1, \
diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
index 07d7385943..e6c5c38d73 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
@@ -1,7 +1,6 @@
chip soc/intel/skylake
# SATA port 0
- register "EnableSata" = "1"
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
register "SataPortsEnable[2]" = "1"
diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
index 91abfe6f03..cd3298fb0c 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
@@ -127,7 +127,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "1" # Enable SSIC for WWAN
- register "EnableSata" = "1"
register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{ \
[0] = 1, \
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index d3ca269492..71102791a6 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -175,7 +175,6 @@ chip soc/intel/skylake
# Must leave UART0 enabled or SD/eMMC will not work as PCI
- register "EnableSata" = "1"
register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{ \
[0] = 1, \
diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb
index dabef4b7e3..b1ffb56d1f 100644
--- a/src/mainboard/libretrend/lt1000/devicetree.cb
+++ b/src/mainboard/libretrend/lt1000/devicetree.cb
@@ -39,7 +39,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
- register "EnableSata" = "1"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "1"
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb
index 5f757e8a04..40f0d19029 100644
--- a/src/mainboard/protectli/vault_kbl/devicetree.cb
+++ b/src/mainboard/protectli/vault_kbl/devicetree.cb
@@ -35,7 +35,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
- register "EnableSata" = "1"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "EnableAzalia" = "0"
diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb
index 51f6ba495a..6e24f5a87d 100644
--- a/src/mainboard/purism/librem_skl/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/devicetree.cb
@@ -46,7 +46,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
- register "EnableSata" = "1"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "1"
diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
index dc7c42b714..9a1ca31f57 100644
--- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
+++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
@@ -28,7 +28,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
- register "EnableSata" = "0"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
register "SataPortsEnable[0]" = "0"
diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
index 0447e70097..cf0d6bcb7f 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
@@ -17,7 +17,6 @@ chip soc/intel/skylake
# SATA configuration
register "SataMode" = "KBLFSP_SATA_MODE_AHCI"
- register "EnableSata" = "1"
register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{ \
[0] = 1, \