summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
authorMarco Chen <marcochen@chromium.org>2020-05-28 13:54:39 +0800
committerFurquan Shaikh <furquan@google.com>2020-05-29 18:33:05 +0000
commit0c6abd786df61072f8dd2ec738bb05a5f8375775 (patch)
treefd0f9c241facca8db6e918cb1048836a477994d2 /src/mainboard
parent44e683d6dd4a80426eb12e5e09579d9a05ee7077 (diff)
downloadcoreboot-0c6abd786df61072f8dd2ec738bb05a5f8375775.tar.xz
mb/google/dedede: add new SPD SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16
The first DRAM part supported by SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16 is NT6AP256T32AV-J2 so the SPD content is generally extracted from it's SPD. On the other hand, SPD bytes 4 / 6 / 13 were amended to follow SoC's requirement. BUG=b:152277273 BRANCH=None TEST=build the image successfully. Change-Id: If6fb0855a961d1c68315a727466bf45569cf2597 Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41813 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/dedede/spd/SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16.spd.hex32
-rw-r--r--src/mainboard/google/dedede/variants/waddledee/Makefile.inc2
2 files changed, 33 insertions, 1 deletions
diff --git a/src/mainboard/google/dedede/spd/SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16.spd.hex b/src/mainboard/google/dedede/spd/SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16.spd.hex
new file mode 100644
index 0000000000..ab171f2952
--- /dev/null
+++ b/src/mainboard/google/dedede/spd/SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16.spd.hex
@@ -0,0 +1,32 @@
+23 11 11 0E 14 19 90 08 00 00 00 00 02 22 00 00
+00 00 05 0A 80 54 01 00 89 00 90 A8 90 A0 05 D0
+02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 FB 00 A6 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc
index aaa65e2a2a..1813377292 100644
--- a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc
+++ b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc
@@ -1,7 +1,7 @@
## SPDX-License-Identifier: GPL-2.0-or-later
SPD_SOURCES = SPD_LPDDR4X_200b_8Gb_4267_DDP_1x16 #0b0000
-SPD_SOURCES += empty #0b0001
+SPD_SOURCES += SPD_LPDDR4X_200b_4Gb_3733_DDP_1x16 #0b0001
romstage-y += memory.c