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authorGaggery Tsai <gaggery.tsai@intel.com>2018-08-01 14:07:18 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-08-03 08:04:58 +0000
commit177f343bccb0fde2fd1f1c5be035cb73d43eb99b (patch)
tree7b9a9c05e2a9ef0a5b9d46298f2c047e871ec57d /src/mainboard
parent32912997bc0324383f82958358b360ac1df3e243 (diff)
downloadcoreboot-177f343bccb0fde2fd1f1c5be035cb73d43eb99b.tar.xz
mb/google/poppy/variants/atlas: Apply correct AC/DC loadlines
This patch applies correct AC/DC loadline settings for Atlas from VRTT report. BUG=b:111419622 BRANCH=None TEST=emerge-atlas coreboot chromeos-bootimage and use DbC to check the AC/DC loadline settgins. Change-Id: I6e85b885a6d3a1db9a980d12f3cfc036a771422a Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/27788 Reviewed-by: Caveh Jalali <caveh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/poppy/variants/atlas/devicetree.cb18
1 files changed, 9 insertions, 9 deletions
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index f6610dfb12..f2c2a12198 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -88,8 +88,8 @@ chip soc/intel/skylake
#| ImonOffset | 0 | 0 | 0 | 0 |
#| IccMax | 4A | 24A | 24A | 24A |
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
- #| AcLoadline | 14.9 | 5 | 5.7 | 4.57 |
- #| DcLoadline | 14.2 | 4.86 | 4.2 | 4.3 |
+ #| AcLoadline | 14.75 | 4.42 | 4.7 | 4.7 |
+ #| DcLoadline | 14.2 | 4.2 | 4.41 | 4.41 |
#+----------------+-------+-------+-------+-------+
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
.vr_config_enable = 1,
@@ -102,7 +102,7 @@ chip soc/intel/skylake
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(4),
.voltage_limit = 1520,
- .ac_loadline = 1490,
+ .ac_loadline = 1475,
.dc_loadline = 1420,
}"
@@ -117,8 +117,8 @@ chip soc/intel/skylake
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(24),
.voltage_limit = 1520,
- .ac_loadline = 500,
- .dc_loadline = 486,
+ .ac_loadline = 442,
+ .dc_loadline = 420,
}"
register "domain_vr_config[VR_GT_UNSLICED]" = "{
@@ -132,8 +132,8 @@ chip soc/intel/skylake
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(24),
.voltage_limit = 1520,
- .ac_loadline = 570,
- .dc_loadline = 420,
+ .ac_loadline = 470,
+ .dc_loadline = 441,
}"
register "domain_vr_config[VR_GT_SLICED]" = "{
@@ -147,8 +147,8 @@ chip soc/intel/skylake
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(24),
.voltage_limit = 1520,
- .ac_loadline = 457,
- .dc_loadline = 430,
+ .ac_loadline = 470,
+ .dc_loadline = 441,
}"
# PCIe Root port 1 with SRCCLKREQ1#