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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-06-25 11:40:00 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-11 08:59:35 +0100
commit1b7609c0e88ba820dbc2251fad0d994e2b54a154 (patch)
treef6d8d73ade4e1b6e7b5a3385d03f964d20e96c23 /src/mainboard
parent122e5bc6b1e551dd79035d26d943283e4cb7b2d7 (diff)
downloadcoreboot-1b7609c0e88ba820dbc2251fad0d994e2b54a154.tar.xz
intel/nehalem: Use romstage_handoff for S3
Don't use scratchpad registers when we have romstage_handoff to pass S3 resume flag. Also fixes console log from reporting early in ramstage "Normal boot" while on S3 resume path. Change-Id: I2f1f05ef4fc640face3d9dc92d12cfe4ba852566 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17676 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/lenovo/x201/mainboard.c5
-rw-r--r--src/mainboard/lenovo/x201/romstage.c18
-rw-r--r--src/mainboard/packardbell/ms2290/romstage.c18
3 files changed, 14 insertions, 27 deletions
diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c
index 2f35c818f5..6c5f9c957f 100644
--- a/src/mainboard/lenovo/x201/mainboard.c
+++ b/src/mainboard/lenovo/x201/mainboard.c
@@ -18,6 +18,7 @@
#include <console/console.h>
#include <device/device.h>
+#include <arch/acpi.h>
#include <arch/io.h>
#include <delay.h>
#include <string.h>
@@ -90,7 +91,6 @@ static void fill_ssdt(device_t device)
static void mainboard_enable(device_t dev)
{
- device_t dev0;
u16 pmbase;
dev->ops->init = mainboard_init;
@@ -110,8 +110,7 @@ static void mainboard_enable(device_t dev)
0x10);
/* If we're resuming from suspend, blink suspend LED */
- dev0 = dev_find_slot(0, PCI_DEVFN(0, 0));
- if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC)
+ if (acpi_is_wakeup_s3())
ec_write(0x0c, 0xc7);
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2);
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index 2bfa19c412..107cc46fc8 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -26,6 +26,7 @@
#include <cpu/x86/lapic.h>
#include <lib.h>
#include <pc80/mc146818rtc.h>
+#include <romstage_handoff.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
@@ -277,20 +278,13 @@ void mainboard_romstage_entry(unsigned long bist)
outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
}
-#if CONFIG_HAVE_ACPI_RESUME
- /* If there is no high memory area, we didn't boot before, so
- * this is not a resume. In that case we just create the cbmem toc.
- */
- if (s3resume) {
- acpi_prepare_for_resume();
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
- } else {
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
+ romstage_handoff_init(s3resume);
+
+ if (s3resume)
+ acpi_prepare_for_resume();
+ else
quick_ram_check();
- }
-#endif
#if CONFIG_LPC_TPM
init_tpm(s3resume);
diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c
index 92ee021caf..42b345ed81 100644
--- a/src/mainboard/packardbell/ms2290/romstage.c
+++ b/src/mainboard/packardbell/ms2290/romstage.c
@@ -26,6 +26,7 @@
#include <cpu/x86/lapic.h>
#include <lib.h>
#include <pc80/mc146818rtc.h>
+#include <romstage_handoff.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
@@ -267,18 +268,11 @@ void mainboard_romstage_entry(unsigned long bist)
outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
}
-#if CONFIG_HAVE_ACPI_RESUME
- /* If there is no high memory area, we didn't boot before, so
- * this is not a resume. In that case we just create the cbmem toc.
- */
- if (s3resume) {
- acpi_prepare_for_resume();
- /* Magic for S3 resume */
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
- } else {
- pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
+ romstage_handoff_init(s3resume);
+
+ if (s3resume)
+ acpi_prepare_for_resume();
+ else
quick_ram_check();
- }
-#endif
}