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| author | Nico Huber <nico.h@gmx.de> | 2019-11-17 02:43:08 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-18 11:51:38 +0000 |
| commit | 1d29b7bbceed82a2161e249474086169ac3039f4 (patch) | |
| tree | 512f36ac5a848a1cef7fef5e0e782e1ca57035a9 /src/mainboard | |
| parent | 6b7b016b6006feb22b48a44b25fd71f1f39ad9cb (diff) | |
| download | coreboot-1d29b7bbceed82a2161e249474086169ac3039f4.tar.xz | |
mb/intel/dcp847ske: Disable xHCI via devicetree
This is supported by generic PCH code now.
Change-Id: Id5d764c97e47cdb08a68d03002ebebd996769914
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/intel/dcp847ske/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/dcp847ske/early_southbridge.c | 2 |
2 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb index ac152d85f9..6ed7c03120 100644 --- a/src/mainboard/intel/dcp847ske/devicetree.cb +++ b/src/mainboard/intel/dcp847ske/devicetree.cb @@ -39,6 +39,7 @@ chip northbridge/intel/sandybridge register "gen1_dec" = "0x00fc0a01" # SuperIO @0xa00-0xaff + device pci 14.0 off end # USB xHCI device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 53f5564a97..1f76db8e52 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -31,7 +31,7 @@ void mainboard_late_rcba_config(void) { /* Disable devices */ - RCBA32(FD) |= PCH_DISABLE_P2P | PCH_DISABLE_XHCI; + RCBA32(FD) |= PCH_DISABLE_P2P; #if CONFIG(USE_NATIVE_RAMINIT) /* Enable Gigabit Ethernet */ |