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authorDtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>2019-01-16 18:07:46 +0800
committerDuncan Laurie <dlaurie@chromium.org>2019-01-18 04:01:38 +0000
commit1e7d69944d3c406bae4c31ac21e7967681f432a6 (patch)
tree863ae49f5b1a78e890b613b3a4c74885379878dc /src/mainboard
parent9cb2da45d8240de73b2a8677f9874ca947d03c11 (diff)
downloadcoreboot-1e7d69944d3c406bae4c31ac21e7967681f432a6.tar.xz
mb/google/sarien/variants/sarien: Adjust TP/TS/H1 I2C CLK to meet spec
After adjustment on Sarien EVT TouchScreen: 380.7 KHz TouchPad: 379.3 KHz H1: 392.2 KHz BUG=b:122657195 BRANCH=master TEST=emerge-sarien coreboot chromeos-bootimage measure by scope Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I0dd92b054d934b38a17898dc8ce9cc18bda1633f Reviewed-on: https://review.coreboot.org/c/30949 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/sarien/variants/sarien/devicetree.cb10
1 files changed, 6 insertions, 4 deletions
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 4334c45083..59f1f30c88 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -81,17 +81,19 @@ chip soc/intel/cannonlake
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
+ .rise_time_ns = 190,
+ .fall_time_ns = 120,
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
- .rise_time_ns = 176,
- .fall_time_ns = 15,
+ .rise_time_ns = 52,
+ .fall_time_ns = 110,
},
.i2c[4] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
- .rise_time_ns = 280,
- .fall_time_ns = 90,
+ .rise_time_ns = 36,
+ .fall_time_ns = 99,
},
}"