1. vgabios removed, will go to extra repository

2. Rename sisnb.c to sis761.c
3. Delete many mis-definition for sis device in
   src/include/device/pci_ids.h
4. Trim trailing spaces for all files

Signed-off-by: Morgan Tsai <my_tsai@sis.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>                                                                                   
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

11 files changed, 110 insertions, 110 deletions

diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb b/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
index 6974de01bc..e0cf14c5de 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
+++ b/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
@@ -239,15 +239,12 @@ chip northbridge/amd/amdk8/root_complex
 				#  devices on link 0, link 0 == LDT 0
 			        chip southbridge/sis/sis966
 					device pci 0.0 on end   # Northbridge
-					#################################################
-					device pci 1.0 on 			# AGP bridge
+					device pci 1.0 on		# AGP bridge
 					  chip drivers/pci/onboard	# Integrated VGA
 						device pci 0.0 on end
 						register "rom_address" = "0xfff80000"
 					  end
 					end
-					#################################################
-					## device pci 1.0 on end   # PCIE
                 			device pci 2.0 on # LPC
 						chip superio/ite/it8716f
 							device pnp 2e.0 off #  Floppy
@@ -272,12 +269,12 @@ chip northbridge/amd/amdk8/root_complex
                 	                 			io 0x62 = 0x230
                 	                			irq 0x70 = 9
 							end
-                	        			device pnp 2e.5 off #  Keyboard
+                	        			device pnp 2e.5 on #  Keyboard
                 	                 			io 0x60 = 0x60
                 	                 			io 0x62 = 0x64
                 	                			irq 0x70 = 1
 							end
-                	        			device pnp 2e.6 off #  Mouse
+                	        			device pnp 2e.6 on #  Mouse
                 	                			irq 0x70 = 12
 							end
                 	        			device pnp 2e.8 off #  MIDI
@@ -291,30 +288,27 @@ chip northbridge/amd/amdk8/root_complex
 						end
 					end
 
- 					device pci 2.5 on end # IDE (SiS5513)
- 					device pci 2.6 off end # Modem (SiS7013)
- 					device pci 2.7 off end # Audio (SiS7012)
-                			device pci 3.0 on end # USB (SiS7001,USB1.1)
-	                		device pci 3.1 on end # USB (SiS7001,USB1.1)
-	                		device pci 3.3 on end # USB (SiS7002,USB2.0)
-	                		device pci 4.0 on end # NIC (SiS191)
-                			device pci 5.0 on end # SATA (SiS1183)
-                			device pci 6.0 off end # SB PCIE1 (SiS000A)
-                			device pci 7.0 off end # SB PCIE2 (SiS000A)
-        	       			device pci 9.0 off end # PCI E 6
-        	       			device pci a.0 off end # PCI E 5
-        	       			device pci b.0 off end # PCI E 4
-                			device pci c.0 off end # PCI E 3
-                			device pci d.0 off end # PCI E 2
-                			device pci e.0 off end # PCI E 1
-        	       			device pci f.0 on end # Hda
+                                        device pci 2.5 off end # IDE (SiS5513)
+                                        device pci 2.6 off end # Modem (SiS7013)
+                                        device pci 2.7 off end # Audio (SiS7012)
+                                        device pci 3.0 on end # USB (SiS7001,USB1.1)
+                                        device pci 3.1 on end # USB (SiS7001,USB1.1)
+                                        device pci 3.3 on end # USB (SiS7002,USB2.0)
+                                        device pci 4.0 on end # NIC (SiS191)
+                                        device pci 5.0 on end # SATA (SiS1183,IDE Mode)
+                                        device pci 6.0 off end # PCI-E (SiS000A)
+                                        device pci 7.0 off end # PCI-E (SiS000A)
+                                        device pci a.0 off end
+                                        device pci b.0 off end
+                                        device pci c.0 off end
+                                        device pci d.0 off end
+                                        device pci e.0 off end
+                                        device pci f.0 off end # HD Audio (SiS7502)
 
-	                                register "ide0_enable" = "1"
-	                                register "ide1_enable" = "1"
-                	                register "sata0_enable" = "1"
-                        	        register "sata1_enable" = "1"
-				   	#register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
-				   	#register "mac_eeprom_addr" = "0x51"
+                                        register "ide0_enable" = "1"
+                                        register "ide1_enable" = "1"
+                                        register "sata0_enable" = "1"
+                                        register "sata1_enable" = "1"
 				end
 			end #  device pci 18.0
 			device pci 18.0 on end # Link 1
@@ -328,14 +322,14 @@ chip northbridge/amd/amdk8/root_complex
 
 #       chip drivers/generic/debug
 #               device pnp 0.0 off end # chip name
-#                device pnp 0.1 on end # pci_regs_all
-#                device pnp 0.2 on end # mem
-#                device pnp 0.3 off end # cpuid
-#                device pnp 0.4 on end # smbus_regs_all
-#                device pnp 0.5 off end # dual core msr
-#                device pnp 0.6 off end # cache size
+#               device pnp 0.1 on end # pci_regs_all
+#               device pnp 0.2 on end # mem
+#               device pnp 0.3 off end # cpuid
+#               device pnp 0.4 on end # smbus_regs_all
+#               device pnp 0.5 off end # dual core msr
+#               device pnp 0.6 off end # cache size
 #               device pnp 0.7 off end # tsc
-#                device pnp 0.8 off  end # io
-#                device pnp 0.9 off end # io
+#               device pnp 0.8 off  end # io
+#               device pnp 0.9 off end # io
 #       end
 end #root_complex
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Options.lb b/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
index a7832bc078..e081e2b0a2 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
+++ b/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
@@ -1,25 +1,25 @@
-## 
+##
 ## This file is part of the LinuxBIOS project.
-## 
+##
 ## Copyright (C) 2007 AMD
 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
 ## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
 ## Written by Morgan Tsai <my_tsai@sis.com> for SiS.
-## 
+##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
 ## the Free Software Foundation; either version 2 of the License, or
 ## (at your option) any later version.
-## 
+##
 ## This program is distributed in the hope that it will be useful,
 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ## GNU General Public License for more details.
-## 
+##
 ## You should have received a copy of the GNU General Public License
 ## along with this program; if not, write to the Free Software
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
+##
 
 uses HAVE_MP_TABLE
 uses HAVE_PIRQ_TABLE
@@ -197,7 +197,7 @@ default LIFT_BSP_APIC_ID=1
 #CHIP_NAME ?
 default CONFIG_CHIP_NAME=1
 
-#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. 
+#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
 #2G
 #default HW_MEM_HOLE_SIZEK=0x200000
 #1G
@@ -253,8 +253,8 @@ default CONFIG_IOAPIC=1
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="SiS"
-default MAINBOARD_VENDOR="SIS"
+default MAINBOARD_PART_NUMBER="ga_2761gxdk"
+default MAINBOARD_VENDOR="GIGABYTE"
 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1039
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234
 
@@ -294,7 +294,7 @@ default CONFIG_ROM_PAYLOAD = 1
 
 ###
 ### Defaults of options that you may want to override in the target config file
-### 
+###
 
 ##
 ## The default compiler
@@ -304,7 +304,7 @@ default HOSTCC="gcc"
 
 ##
 ## Disable the gdb stub by default
-## 
+##
 default CONFIG_GDB_STUB=0
 
 ##
@@ -335,15 +335,15 @@ default TTYS0_LCS=0x3
 ##
 ### Select the linuxBIOS loglevel
 ##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
+## EMERG      1   system is unusable
+## ALERT      2   action must be taken immediately
+## CRIT       3   critical conditions
+## ERR        4   error conditions
+## WARNING    5   warning conditions
+## NOTICE     6   normal but significant condition
+## INFO       7   informational
+## DEBUG      8   debug-level messages
+## SPEW       9   Way too many details
 
 ## Request this level of debugging output
 default  DEFAULT_CONSOLE_LOGLEVEL=8
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c b/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c
index 7e4eddaa5c..06bb3f26f8 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c
@@ -27,7 +27,7 @@
 #define RAMINIT_SYSINFO 1
 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
-#define SET_NB_CFG_54 1 
+#define SET_NB_CFG_54 1
 
 //used by raminit
 #define QRANK_DIMM_SUPPORT 1
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c b/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c
index 732027adca..b52f1f2e8f 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c
@@ -46,7 +46,7 @@
 #endif
 
 #define DBGP_DEFAULT 7
- 
+
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
@@ -95,7 +95,7 @@
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
-#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) 
+#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
 
 #include "southbridge/sis/sis966/sis966_early_ctrl.c"
 
@@ -126,7 +126,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "sdram/generic_sdram.c"
 
-#include "resourcemap.c" 
+#include "resourcemap.c"
 
 #include "cpu/amd/dualcore/dualcore.c"
 
@@ -171,13 +171,13 @@ static void sio_setup(void)
         uint8_t byte;
 
         byte = pci_read_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b);
-        byte |= 0x20; 
+        byte |= 0x20;
         pci_write_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b, byte);
-        
+
         dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0);
         dword |= (1<<0);
         pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0, dword);
-        
+
         dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4);
         dword |= (1<<16);
         pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4, dword);
@@ -237,15 +237,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if HAVE_FAILOVER_BOOT==1 
+#if HAVE_FAILOVER_BOOT==1
     #if USE_FAILOVER_IMAGE==1
-	failover_process(bist, cpu_init_detectedx);	
+	failover_process(bist, cpu_init_detectedx);
     #else
 	real_main(bist, cpu_init_detectedx);
     #endif
 #else
     #if USE_FALLBACK_IMAGE == 1
-	failover_process(bist, cpu_init_detectedx);	
+	failover_process(bist, cpu_init_detectedx);
     #endif
 	real_main(bist, cpu_init_detectedx);
 #endif
@@ -281,7 +281,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
         setup_mb_resource_map();
 
         uart_init();
-	
+
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
@@ -340,7 +340,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         needs_reset |= optimize_link_coherent_ht();
         needs_reset |= optimize_link_incoherent_ht(sysinfo);
-        needs_reset |= sis966_early_setup_x();
 
         // fidvid change will issue one LDTSTOP and the HT change will be effective too
         if (needs_reset) {
@@ -353,8 +352,8 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 
         sis_init_stage1();
-        enable_smbus(); 
-       
+        enable_smbus();
+
         memreset_setup();
 
         //do we need apci timer, tsc...., only debug need it for better output
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/chip.h b/src/mainboard/gigabyte/ga_2761gxdk/chip.h
index a93dc54917..66ddb8c353 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/chip.h
+++ b/src/mainboard/gigabyte/ga_2761gxdk/chip.h
@@ -1,8 +1,6 @@
 /*
  * This file is part of the LinuxBIOS project.
  *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
  * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
  * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
  *
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout b/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout
index 84a5c52278..9e79be1721 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout
+++ b/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout
@@ -1,23 +1,23 @@
-## 
+##
 ## This file is part of the LinuxBIOS project.
-## 
+##
 ## Copyright (C) 2007 AMD
 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-## 
+##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
 ## the Free Software Foundation; either version 2 of the License, or
 ## (at your option) any later version.
-## 
+##
 ## This program is distributed in the hope that it will be useful,
 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ## GNU General Public License for more details.
-## 
+##
 ## You should have received a copy of the GNU General Public License
 ## along with this program; if not, write to the Free Software
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
+##
 
 entries
 
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c b/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c
index d8b0c0ab5a..acab382ac2 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c
@@ -40,7 +40,7 @@
         unsigned apicid_sis966;
 
 
-unsigned pci1234x[] = 
+unsigned pci1234x[] =
 {        //Here you only need to set value in pci1234 for HT-IO that could be installed or not
 	 //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
         0x0000ff0,
@@ -52,7 +52,7 @@ unsigned pci1234x[] =
 //        0x0000ff0,
 //        0x0000ff0
 };
-unsigned hcdnx[] = 
+unsigned hcdnx[] =
 { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
 	0x20202020,
 //	0x20202020,
@@ -63,7 +63,7 @@ unsigned hcdnx[] =
 //        0x20202020,
 //        0x20202020,
 };
-unsigned bus_type[256]; 
+unsigned bus_type[256];
 
 extern void get_sblk_pci1234(void);
 
@@ -96,13 +96,13 @@ void get_bus_conf(void)
 	for(i=0; i<8; i++) {
 		bus_sis966[i] = 0;
 	}
-	
+
 	for(i=0;i<256; i++) {
 		bus_type[i] = 0;
 	}
 
 	bus_type[0] = 1; //pci
-	
+
 	bus_sis966[0] = (sysconf.pci1234[0] >> 16) & 0xff;
 
 	bus_type[bus_sis966[0]] = 1;
@@ -140,8 +140,8 @@ void get_bus_conf(void)
 /*I/O APICs:	APIC ID	Version	State		Address*/
 #if CONFIG_LOGICAL_CPUS==1
 	apicid_base = get_apicid_base(1);
-#else 
-	apicid_base = CONFIG_MAX_PHYSICAL_CPUS; 
+#else
+	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
 #endif
 	apicid_sis966 = apicid_base+0;
 
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c b/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c
index c87b9d6954..c19c9ac263 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c
@@ -32,7 +32,7 @@
 #include <string.h>
 #include <stdint.h>
 #include <arch/pirq_routing.h>
-
+#include <device/pci_ids.h>
 #include <cpu/amd/amdk8_sysconf.h>
 
 static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
@@ -75,7 +75,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
         addr &= ~15;
 
         /* This table must be betweeen 0xf0000 & 0x100000 */
-        printk_info("Writing IRQ routing tables to 0x%x...", addr);
+        printk_info("Writing IRQ routing tables to 0x%x...\n", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
@@ -88,8 +88,8 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 
 	pirq->exclusive_irqs = 0;
 
-	pirq->rtr_vendor = 0x10de;
-	pirq->rtr_device = 0x0370;
+	pirq->rtr_vendor = PCI_VENDOR_ID_SIS;
+	pirq->rtr_device = PCI_DEVICE_ID_SIS_SIS966_PCI;
 
 	pirq->miniport_data = 0;
 
@@ -124,11 +124,17 @@ unsigned long write_pirq_routing_table(unsigned long addr)
                 }
 
                 printk_debug("Setting Onboard SiS Southbridge\n");
-//                dev = dev_find_slot(0, PCI_DEVFN(2,5));   // 5513 (IDE)
-//                pci_write_config8(dev, 0x3C, 0x0A);
-                dev = dev_find_slot(0, PCI_DEVFN(3,0));   // USB 1.1 -1
+
+                /*
+                 * Non-layout for GA-2761GX
+                 *
+                dev = dev_find_slot(0, PCI_DEVFN(2,5));   // 5513 (IDE)
+                pci_write_config8(dev, 0x3C, 0x0A);
+                */
+
+                dev = dev_find_slot(0, PCI_DEVFN(3,0));   // USB 1.1
                 pci_write_config8(dev, 0x3C, 0x0B);
-                dev = dev_find_slot(0, PCI_DEVFN(3,1));   // USB 1.1 -2
+                dev = dev_find_slot(0, PCI_DEVFN(3,1));   // USB 1.1
                 pci_write_config8(dev, 0x3C, 0x05);
                 dev = dev_find_slot(0, PCI_DEVFN(3,3));   // USB 2.0
                 pci_write_config8(dev, 0x3C, 0x0A);
@@ -136,12 +142,17 @@ unsigned long write_pirq_routing_table(unsigned long addr)
                 pci_write_config8(dev, 0x3C, 0x05);
                 dev = dev_find_slot(0, PCI_DEVFN(5,0));    // 1183 (SATA)
                 pci_write_config8(dev, 0x3C, 0x0B);
-//                dev = dev_find_slot(0, PCI_DEVFN(6,0));   // PCI-E
-//                pci_write_config8(dev, 0x3C, 0x0A);
-//                dev = dev_find_slot(0, PCI_DEVFN(7,0));   // PCI-E
-//                pci_write_config8(dev, 0x3C, 0x0A);
+
+                /*
+                 * Non-layout for GA-2761GX
+                 *
+                dev = dev_find_slot(0, PCI_DEVFN(6,0));   // PCI-E
+                pci_write_config8(dev, 0x3C, 0x0A);
+                dev = dev_find_slot(0, PCI_DEVFN(7,0));   // PCI-E
+                pci_write_config8(dev, 0x3C, 0x0A);
                 dev = dev_find_slot(0, PCI_DEVFN(15,0));  // Azalia
                 pci_write_config8(dev, 0x3C, 0x05);
+                */
         }
 
 //pci bridge
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c b/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c
index b8b6a189f9..bc448f136d 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c
@@ -1,8 +1,6 @@
 /*
  * This file is part of the LinuxBIOS project.
  *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
  * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
  * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
  *
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
index ab54d0c361..70dc525add 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
@@ -33,7 +33,7 @@ extern unsigned char bus_sis966[8]; //1
 
 extern unsigned apicid_sis966;
 
-extern unsigned bus_type[256]; 
+extern unsigned bus_type[256];
 
 void *smp_write_config_table(void *v)
 {
@@ -80,7 +80,7 @@ void *smp_write_config_table(void *v)
                 device_t dev;
 		struct resource *res;
 		uint32_t dword;
- 
+
                 dev = dev_find_slot(bus_sis966[0], PCI_DEVFN(sbdn+ 0x1,0));
                 if (dev) {
 			res = find_resource(dev, PCI_BASE_ADDRESS_1);
@@ -99,7 +99,7 @@ void *smp_write_config_table(void *v)
 
                 }
 	}
-  
+
 /*I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#
 */	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sis966, 0x0);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x1, apicid_sis966, 0x1);
@@ -135,7 +135,7 @@ void *smp_write_config_table(void *v)
         	}
 	}
 
-	for(j=0; j<2; j++) 
+	for(j=0; j<2; j++)
 	        for(i=0;i<4;i++) {
         	        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[1], ((0x06+j)<<2)|i, apicid_sis966, 0x10 + (2+i+j)%4);
 	        }
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c b/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c
index 7e23ad9cc9..8d30b5e052 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c
@@ -161,7 +161,7 @@ static void setup_mb_resource_map(void)
 		 *	   1 = base/limit registers i are read-only
 		 * [ 7: 4] Reserved
 		 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
-		 *	   This field defines the upper address bits of a 40bit address 
+		 *	   This field defines the upper address bits of a 40bit address
 		 *	   that defines the start of memory-mapped I/O region i
 		 */
 		PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
@@ -199,7 +199,7 @@ static void setup_mb_resource_map(void)
 		 * [31:25] Reserved
 		 */
 //		PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
-		PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, 
+		PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
 
@@ -217,7 +217,7 @@ static void setup_mb_resource_map(void)
 		 * [ 3: 2] Reserved
 		 * [ 4: 4] VGA Enable
 		 *	   0 = VGA matches Disabled
-		 *	   1 = matches all address < 64K and where A[9:0] is in the 
+		 *	   1 = matches all address < 64K and where A[9:0] is in the
 		 *	       range 3B0-3BB or 3C0-3DF independen of the base & limit registers
 		 * [ 5: 5] ISA Enable
 		 *	   0 = ISA matches Disabled
@@ -225,7 +225,7 @@ static void setup_mb_resource_map(void)
 		 *	       from matching agains this base/limit pair
 		 * [11: 6] Reserved
 		 * [24:12] PCI I/O Base i
-		 *	   This field defines the start of PCI I/O region n 
+		 *	   This field defines the start of PCI I/O region n
 		 * [31:25] Reserved
 		 */
 //		PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
@@ -270,9 +270,9 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the highest bus number in configuration region i
 		 */
 //		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */
-		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, 
+		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, 
+		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
 
 	};