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authorMyles Watson <mylesgw@gmail.com>2009-10-13 22:53:24 +0000
committerMyles Watson <mylesgw@gmail.com>2009-10-13 22:53:24 +0000
commit21ee98bf79c00b3b5693f2ce43d98fa8335589d4 (patch)
treecf5fbc65b5c56fbc4e5c2e65ff854752e0bb8f63 /src/mainboard
parentfbc11edd7ac806516ebd301ee721035706eb4541 (diff)
downloadcoreboot-21ee98bf79c00b3b5693f2ce43d98fa8335589d4.tar.xz
White space change in preparation for a patch to unify handling of ck804.
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4770 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/tyan/s2892/cache_as_ram_auto.c16
-rw-r--r--src/mainboard/tyan/s2895/cache_as_ram_auto.c19
2 files changed, 9 insertions, 26 deletions
diff --git a/src/mainboard/tyan/s2892/cache_as_ram_auto.c b/src/mainboard/tyan/s2892/cache_as_ram_auto.c
index 3d72b75a3f..a28d4a9957 100644
--- a/src/mainboard/tyan/s2892/cache_as_ram_auto.c
+++ b/src/mainboard/tyan/s2892/cache_as_ram_auto.c
@@ -70,10 +70,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
//set GPIO to input mode
#define CK804_MB_SETUP \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
+ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
#include "southbridge/nvidia/ck804/ck804_early_setup.c"
@@ -154,12 +154,10 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
-
-#if CONFIG_USE_FALLBACK_IMAGE == 1
- failover_process(bist, cpu_init_detectedx);
-#endif
+ #if CONFIG_USE_FALLBACK_IMAGE == 1
+ failover_process(bist, cpu_init_detectedx);
+ #endif
real_main(bist, cpu_init_detectedx);
-
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
diff --git a/src/mainboard/tyan/s2895/cache_as_ram_auto.c b/src/mainboard/tyan/s2895/cache_as_ram_auto.c
index 74109cda7f..a15dc0b184 100644
--- a/src/mainboard/tyan/s2895/cache_as_ram_auto.c
+++ b/src/mainboard/tyan/s2895/cache_as_ram_auto.c
@@ -95,7 +95,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/dualcore/dualcore.c"
#define CK804_NUM 2
-#define CK804B_BUSN 0x80
#define CK804_USE_NIC 1
#define CK804_USE_ACI 1
@@ -279,8 +278,8 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ck804_early_setup_x();
if (needs_reset) {
- print_info("ht reset -\r\n");
- // soft_reset();
+ printk_info("ht reset -\r\n");
+ soft_reset();
}
allow_all_aps_stop(bsp_apicid);
@@ -290,24 +289,10 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
fill_mem_ctrl(nodes, ctrl, spd_addr);
enable_smbus();
-#if 0
- dump_spd_registers(&cpu[0]);
-#endif
-#if 0
- dump_smbus_registers();
-#endif
memreset_setup();
sdram_initialize(nodes, ctrl);
-#if 0
- print_pci_devices();
-#endif
-
-#if 0
- dump_pci_devices();
-#endif
-
post_cache_as_ram();
}
#endif