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authorRonald G. Minnich <rminnich@gmail.com>2006-06-18 02:28:07 +0000
committerRonald G. Minnich <rminnich@gmail.com>2006-06-18 02:28:07 +0000
commit2d7bb590187052e96113d45378f0182f7d692e40 (patch)
tree61848154f3af306da0b04a2689ac7e6b5f9782bc /src/mainboard
parent48415d5cf6f317aa7d7c30623ed2b36b29710d8e (diff)
downloadcoreboot-2d7bb590187052e96113d45378f0182f7d692e40.tar.xz
fix idiiot typo I did not catch.
add support for conditional enable of uarta interrupt. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/olpc/rev_a/Config.lb3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/olpc/rev_a/Config.lb b/src/mainboard/olpc/rev_a/Config.lb
index 98ff136b82..e0e2613b30 100644
--- a/src/mainboard/olpc/rev_a/Config.lb
+++ b/src/mainboard/olpc/rev_a/Config.lb
@@ -124,7 +124,7 @@ dir /pc80
config chip.h
chip northbridge/amd/gx2
- register "irq_map" = "0xaa5b";
+ register "irqmap" = "0xaa5b"
device apic_cluster 0 on
chip cpu/amd/model_gx2
device apic 0 on end
@@ -136,6 +136,7 @@ chip northbridge/amd/gx2
chip southbridge/amd/cs5536
register "enable_gpio0_inta" = "1"
register "enable_ide_nand_flash" = "1"
+ register "enable_uarta" = "1"
device pci d.0 on end # Realtek 8139 LAN
device pci f.0 on end # ISA Bridge
device pci f.2 on end # IDE Controller