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authorDaniel Kurtz <djkurtz@chromium.org>2019-01-18 16:50:58 -0700
committerMartin Roth <martinroth@google.com>2019-01-22 18:55:09 +0000
commit2ea99da49de6d7faa499510b2d747532be776172 (patch)
tree2454057a4953e3e1c670982c0964e8d318bfff06 /src/mainboard
parent69f6fd4589ee4d7cb0bfa12face26eba1fa0a973 (diff)
downloadcoreboot-2ea99da49de6d7faa499510b2d747532be776172.tar.xz
Revert "UPSTREAM: mainboard/google/kahlee: Also configure GPIO_9 in RAM stage"
This reverts commit 3278f859c3dd97a6d6d885a91dfd33d44e95d58b. Reason for revert: It turns out all we want to set in RAM stage is GPIO's DEBOUNCE config, not its SCI configuration. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> BUG=b:113880780 BRANCH=none TEST=Boot grunt, does not go to recovery screen Change-Id: I500934f3e03e66c97873accd4a979a23d4509675 Reviewed-on: https://review.coreboot.org/c/30997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/kahlee/variants/baseboard/gpio.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
index 399c78c162..e9ae28c25b 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
@@ -117,9 +117,6 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
/* GPIO_8 - DDR_ALERT_3V3_L (currently not used) */
PAD_GPI(GPIO_8, PULL_UP),
- /* GPIO_9 - H1_PCH_INT_ODL, SCI */
- PAD_SCI(GPIO_9, PULL_UP, EDGE_LOW),
-
/* GPIO_10 - SLP_S0_L (currently not used) */
PAD_NF(GPIO_10, S0A3_GPIO, PULL_UP),