diff options
| author | Wisley Chen <wisley.chen@quanta.corp-partner.google.com> | 2020-04-21 17:48:10 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-04-27 16:13:07 +0000 |
| commit | 2f7f0c62fdacde2b7960c58f8608066f23a8c79b (patch) | |
| tree | 93603a4938580282b020b7f66ed71e4509cf0c52 /src/mainboard | |
| parent | 2f58a007a7528090454d3384bacc973c503b4d20 (diff) | |
| download | coreboot-2f7f0c62fdacde2b7960c58f8608066f23a8c79b.tar.xz | |
mb/google/hatch/var/jinlon: Update DPTF parameters
The change applies the DPTF parameters received from the thermal team.
1. Set PL1 Min to 3W
2. Set sample period of TCPU/TSR0/TSR1 to 30 Sec
3. Enable EC_ENABLE_MULTIPLE_DPTF_PROFILES and add trigger points
for tablet mode.
4. Update trigger points of CPU/TSR0/TSR1
BUG=b:154564062, b:154290855
BRANCH=hatch
TEST=build and verified by thermal team.
Change-Id: I87170e63de222487a3bda1217c4ee87a2ec1984f
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl | 24 | ||||
| -rw-r--r-- | src/mainboard/google/hatch/variants/jinlon/include/variant/ec.h | 1 |
2 files changed, 15 insertions, 10 deletions
diff --git a/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl index 7824d11776..ddb11efc1a 100644 --- a/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/jinlon/include/variant/acpi/dptf.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -#define DPTF_CPU_PASSIVE 70 +#define DPTF_CPU_PASSIVE 77 #define DPTF_CPU_CRITICAL 105 #define DPTF_CPU_ACTIVE_AC0 70 #define DPTF_CPU_ACTIVE_AC1 65 @@ -11,13 +11,17 @@ #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" -#define DPTF_TSR0_PASSIVE 62 +#define DPTF_TSR0_PASSIVE 58 #define DPTF_TSR0_CRITICAL 105 +#define DPTF_TSR0_TABLET_PASSIVE 58 +#define DPTF_TSR0_TABLET_CRITICAL 105 #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" -#define DPTF_TSR1_PASSIVE 54 -#define DPTF_TSR1_CRITICAL 105 +#define DPTF_TSR1_PASSIVE 57 +#define DPTF_TSR1_CRITICAL 86 +#define DPTF_TSR1_TABLET_PASSIVE 49 +#define DPTF_TSR1_TABLET_CRITICAL 86 #define DPTF_ENABLE_CHARGER @@ -31,13 +35,13 @@ Name (CHPS, Package () { Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 300, 0, 0, 0, 0 }, - /* CPU Throttle Effect on Ambient (TSR0) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + /* CPU Throttle Effect on Ambient (TSR1) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 300, 0, 0, 0, 0 }, - /* Charger Throttle Effect on Charger (TSR1) */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, + /* Charger Throttle Effect on Charger (TSR0) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 300, 0, 0, 0, 0 }, }) Name (MPPC, Package () @@ -45,7 +49,7 @@ Name (MPPC, Package () 0x2, /* Revision */ Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 12000, /* PowerLimitMinimum */ + 3000, /* PowerLimitMinimum */ 15000, /* PowerLimitMaximum */ 28000, /* TimeWindowMinimum */ 32000, /* TimeWindowMaximum */ diff --git a/src/mainboard/google/hatch/variants/jinlon/include/variant/ec.h b/src/mainboard/google/hatch/variants/jinlon/include/variant/ec.h index 54877da690..c947821e2b 100644 --- a/src/mainboard/google/hatch/variants/jinlon/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/jinlon/include/variant/ec.h @@ -5,5 +5,6 @@ #define VARIANT_EC_H #include <baseboard/ec.h> +#define EC_ENABLE_MULTIPLE_DPTF_PROFILES #endif |