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authorAngel Pons <th3fanbus@gmail.com>2020-04-27 00:16:59 +0200
committerFelix Held <felix-coreboot@felixheld.de>2020-05-02 18:58:05 +0000
commit3a3fb365a912d34d2cb3afdb5bd704ae4eaa0a59 (patch)
tree26acc828f600a572711c4150eee74ac160490f85 /src/mainboard
parentfada3e56c4d896bcbf41280f0d20ed7c72000890 (diff)
downloadcoreboot-3a3fb365a912d34d2cb3afdb5bd704ae4eaa0a59.tar.xz
mb/asus/p8h61-m_pro: Disable SB-TSI base address
SB-TSI is specific to AMD platforms, but this is an Intel board. Change-Id: I5eb7e3bc920103279dfca3a9ec14a41666404993 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40738 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/asus/p8h61-m_pro/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb
index ce6acadb8e..2d1550da3c 100644
--- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb
+++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb
@@ -95,7 +95,7 @@ chip northbridge/intel/sandybridge
end
device pnp 2e.b on # HWM, LED
io 0x60 = 0x0290
- io 0x62 = 0x0200
+ io 0x62 = 0x0000
end
device pnp 2e.d on end # VID
device pnp 2e.e off end # CIR WAKE-UP