diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2018-11-20 14:32:58 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-06-09 02:47:55 +0000 |
| commit | 4b8f5a351799dd22d8924b8bea4a3e666893f965 (patch) | |
| tree | 891b155595418bf32f5a76c8cf2be0ee4440bbb7 /src/mainboard | |
| parent | 2ee8fe0094da413fe57796131d7c3b9f927f68a1 (diff) | |
| download | coreboot-4b8f5a351799dd22d8924b8bea4a3e666893f965.tar.xz | |
mb/google/dragonegg: Pass FSP-M UPD as per dragonegg requirement
TEST=Able to boot dragonegg board with LPDDR4 memory.
Change-Id: Idbe0aa79879f2b1a754dd1f6718ad4ba1173e760
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31956
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/dragonegg/romstage_fsp_params.c | 65 | ||||
| -rw-r--r-- | src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb | 4 |
2 files changed, 67 insertions, 2 deletions
diff --git a/src/mainboard/google/dragonegg/romstage_fsp_params.c b/src/mainboard/google/dragonegg/romstage_fsp_params.c index f2c6851a3f..f1f5143ab5 100644 --- a/src/mainboard/google/dragonegg/romstage_fsp_params.c +++ b/src/mainboard/google/dragonegg/romstage_fsp_params.c @@ -13,9 +13,74 @@ * GNU General Public License for more details. */ +#include <assert.h> #include <baseboard/variants.h> +#include <cbfs.h> +#include <console/console.h> #include <soc/romstage.h> +static uintptr_t mainboard_get_spd_data(void) +{ + char *spd_file; + size_t spd_file_len; + int spd_index; + const size_t spd_len = CONFIG_DIMM_SPD_SIZE; + const char *spd_bin = "spd.bin"; + + spd_index = variant_memory_sku(); + assert(spd_index >= 0); + printk(BIOS_INFO, "SPD index %d\n", spd_index); + + /* Load SPD data from CBFS */ + spd_file = cbfs_boot_map_with_leak(spd_bin, CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + /* make sure we have at least one SPD in the file. */ + if (spd_file_len < spd_len) + die("Missing SPD data."); + + /* Make sure we did not overrun the buffer */ + if (spd_file_len < ((spd_index + 1) * spd_len)) + die("Invalid SPD index."); + + spd_index *= spd_len; + + return (uintptr_t)(spd_file + spd_index); +} + void mainboard_memory_init_params(FSPM_UPD *mupd) { + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + struct lpddr4_config mem_params; + + memset(&mem_params, 0, sizeof(mem_params)); + variant_memory_params(&mem_params); + + if (mem_params.dq_map && mem_params.dq_map_size) + memcpy(&mem_cfg->DqByteMapCh0, mem_params.dq_map, + mem_params.dq_map_size); + + if (mem_params.dqs_map && mem_params.dqs_map_size) + memcpy(&mem_cfg->DqsMapCpu2DramCh0, mem_params.dqs_map, + mem_params.dqs_map_size); + + memcpy(&mem_cfg->RcompResistor, mem_params.rcomp_resistor, + mem_params.rcomp_resistor_size); + + memcpy(&mem_cfg->RcompTarget, mem_params.rcomp_target, + mem_params.rcomp_target_size); + + mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->CaVrefConfig = 0x2; + mem_cfg->ECT = 1; /* Early Command Training Enabled */ + mem_cfg->RefClk = 0; /* Auto Select CLK freq */ + mem_cfg->SpdAddressTable[0] = 0x0; + mem_cfg->SpdAddressTable[1] = 0x0; + mem_cfg->SpdAddressTable[2] = 0x0; + mem_cfg->SpdAddressTable[3] = 0x0; } diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb index f820924280..b3b93f55ca 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb @@ -102,8 +102,8 @@ chip soc/intel/icelake [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, - [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoSkipInit, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, }" register "SerialIoGSpiMode" = "{ |