diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-01-17 15:27:18 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-01-18 20:43:25 +0000 |
| commit | 4c65398c10fa4583ad6b83ddc7f7873625a6ddbf (patch) | |
| tree | 231111b2f558d99ddb06f9bb7cb45564c9b72e98 /src/mainboard | |
| parent | a9d4e2adce13ac467647caa0449726844016aa39 (diff) | |
| download | coreboot-4c65398c10fa4583ad6b83ddc7f7873625a6ddbf.tar.xz | |
Intel i82810 boards & chips: Remove - using LATE_CBMEM_INIT
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
northbridge/intel/i82810
Mainboards:
src/mainboard/asus/mew-am
src/mainboard/asus/mew-vm
src/mainboard/ecs/p6iwp-fe
src/mainboard/hp/e_vectra_p2706t
src/mainboard/intel/d810e2cb
src/mainboard/mitac/6513wu
src/mainboard/msi/ms6178
src/mainboard/nec/powermate2000
Change-Id: Ib273316c59f499e6cd3a0e4c4dc4c2cce94ff291
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/23300
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
56 files changed, 0 insertions, 1973 deletions
diff --git a/src/mainboard/asus/mew-am/Kconfig b/src/mainboard/asus/mew-am/Kconfig deleted file mode 100644 index 938dfde2b7..0000000000 --- a/src/mainboard/asus/mew-am/Kconfig +++ /dev/null @@ -1,38 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_ASUS_MEW_AM - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_INTEL_SOCKET_PGA370 - select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801AX - select SUPERIO_SMSC_SMSCSUPERIO - select HAVE_PIRQ_TABLE - select BOARD_ROMSIZE_KB_512 - -config MAINBOARD_DIR - string - default asus/mew-am - -config MAINBOARD_PART_NUMBER - string - default "MEW-AM" - -config IRQ_SLOT_COUNT - int - default 8 - -endif # BOARD_ASUS_MEW_AM diff --git a/src/mainboard/asus/mew-am/Kconfig.name b/src/mainboard/asus/mew-am/Kconfig.name deleted file mode 100644 index 819e73bfe0..0000000000 --- a/src/mainboard/asus/mew-am/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_MEW_AM - bool "MEW-AM" diff --git a/src/mainboard/asus/mew-am/board_info.txt b/src/mainboard/asus/mew-am/board_info.txt deleted file mode 100644 index 1102fad96f..0000000000 --- a/src/mainboard/asus/mew-am/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Category: desktop -Board URL: ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/ -ROM package: PLCC -ROM socketed: y -Flashrom support: n -Release year: 2004 diff --git a/src/mainboard/asus/mew-am/devicetree.cb b/src/mainboard/asus/mew-am/devicetree.cb deleted file mode 100644 index 8a20cab8a1..0000000000 --- a/src/mainboard/asus/mew-am/devicetree.cb +++ /dev/null @@ -1,60 +0,0 @@ -chip northbridge/intel/i82810 # Northbridge - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # CPU - device lapic 0 on end # APIC - end - end - device domain 0 on # PCI domain - device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) - device pci 1.0 on end # Chipset Graphics Controller (CGC) - chip southbridge/intel/i82801ax # Southbridge - register "ide0_enable" = "1" - register "ide1_enable" = "1" - - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA bridge - chip superio/smsc/smscsuperio # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 4 - end - device pnp 2e.4 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.7 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 2e.9 on # Game port - io 0x60 = 0x201 - end - device pnp 2e.a on # Power-management events (PME) - io 0x60 = 0x600 - end - device pnp 2e.b on # MIDI port (MPU-401) - io 0x60 = 0x330 - irq 0x70 = 5 - end - end - end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMbus - device pci 1f.5 off end # AC'97 audio (N/A, uses CS4280 chip) - device pci 1f.6 off end # AC'97 modem (N/A) - end - end -end diff --git a/src/mainboard/asus/mew-am/irq_tables.c b/src/mainboard/asus/mew-am/irq_tables.c deleted file mode 100644 index 4af829baa8..0000000000 --- a/src/mainboard/asus/mew-am/irq_tables.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, - PIRQ_VERSION, - 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x1f << 3) | 0x0, /* Interrupt router device */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x122e, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xe3, /* Checksum */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x1e << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, - {0x01,(0x08 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, - {0x01,(0x09 << 3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, - {0x01,(0x0a << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, - {0x01,(0x0b << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, - {0x00,(0x1f << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, - {0x00,(0x01 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, - {0x01,(0x02 << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/asus/mew-am/romstage.c b/src/mainboard/asus/mew-am/romstage.c deleted file mode 100644 index c39657b4e0..0000000000 --- a/src/mainboard/asus/mew-am/romstage.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stdlib.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <console/console.h> -#include <southbridge/intel/i82801ax/i82801ax.h> -#include <northbridge/intel/i82810/raminit.h> -#include <cpu/x86/bist.h> -#include <cpu/intel/romstage.h> -#include <superio/smsc/smscsuperio/smscsuperio.h> -#include <lib.h> - -#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) - -void mainboard_romstage_entry(unsigned long bist) -{ - smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - report_bist_failure(bist); - enable_smbus(); - dump_spd_registers(); - sdram_set_registers(); - sdram_set_spd_registers(); - sdram_enable(); -} diff --git a/src/mainboard/asus/mew-vm/Kconfig b/src/mainboard/asus/mew-vm/Kconfig deleted file mode 100644 index 91a9c8b231..0000000000 --- a/src/mainboard/asus/mew-vm/Kconfig +++ /dev/null @@ -1,39 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_ASUS_MEW_VM - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_INTEL_SOCKET_PGA370 - select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801AX - select SUPERIO_SMSC_LPC47B272 - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select BOARD_ROMSIZE_KB_512 - -config MAINBOARD_DIR - string - default asus/mew-vm - -config MAINBOARD_PART_NUMBER - string - default "MEW-VM" - -config IRQ_SLOT_COUNT - int - default 11 - -endif # BOARD_ASUS_MEW_VM diff --git a/src/mainboard/asus/mew-vm/Kconfig.name b/src/mainboard/asus/mew-vm/Kconfig.name deleted file mode 100644 index 4966679acb..0000000000 --- a/src/mainboard/asus/mew-vm/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_MEW_VM - bool "MEW-VM" diff --git a/src/mainboard/asus/mew-vm/board_info.txt b/src/mainboard/asus/mew-vm/board_info.txt deleted file mode 100644 index cbb761aa3f..0000000000 --- a/src/mainboard/asus/mew-vm/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Category: desktop -Board URL: http://www.elhvb.com/mboards/OEM/HP/manual/ASUS%20MEW-VM.htm -ROM package: PLCC -ROM socketed: y -Flashrom support: n -Release year: 2002 diff --git a/src/mainboard/asus/mew-vm/cmos.layout b/src/mainboard/asus/mew-vm/cmos.layout deleted file mode 100644 index b8ea9363a4..0000000000 --- a/src/mainboard/asus/mew-vm/cmos.layout +++ /dev/null @@ -1,28 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -456 1 e 1 ECC_memory -1008 16 h 0 check_sum - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew - -checksums - -checksum 392 1007 1008 diff --git a/src/mainboard/asus/mew-vm/devicetree.cb b/src/mainboard/asus/mew-vm/devicetree.cb deleted file mode 100644 index 397b9993d0..0000000000 --- a/src/mainboard/asus/mew-vm/devicetree.cb +++ /dev/null @@ -1,51 +0,0 @@ -chip northbridge/intel/i82810 - device domain 0 on - device pci 0.0 on end # Host bridge - device pci 1.0 on # Onboard Video - # device pci 1.0 on end - end - chip southbridge/intel/i82801ax # Southbridge - register "ide0_enable" = "1" - register "ide1_enable" = "1" - - device pci 1e.0 on # PCI Bridge - # device pci 1.0 on end - end - device pci 1f.0 on # ISA/LPC? Bridge - chip superio/smsc/lpc47b272 - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.7 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # Keyboard interrupt - irq 0x72 = 12 # Mouse interrupt - end - device pnp 2e.a off end # ACPI - end - end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # AC'97, no header on MEW-VM - device pci 1f.6 off end # AC'97 Modem (MC'97) - end - end - chip cpu/intel/socket_PGA370 - end -end diff --git a/src/mainboard/asus/mew-vm/irq_tables.c b/src/mainboard/asus/mew-vm/irq_tables.c deleted file mode 100644 index 7ebc2d53d6..0000000000 --- a/src/mainboard/asus/mew-vm/irq_tables.c +++ /dev/null @@ -1,35 +0,0 @@ -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ - 0x00, /* Where the interrupt router lies (bus) */ - (0x11 << 3)|0x0, /* Where the interrupt router lies (dev) */ - 0xe20, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x7120, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x89, /* u8 checksum , this has to set to some value -that would give 0 after the sum of all bytes for this structure (including checksum) */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x08 << 3)|0x0, {{0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0xdea0}, {0x01, 0x0dea0}}, 0x1, 0x0}, - {0x00,(0x09 << 3)|0x0, {{0x03, 0xdea0}, {0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0x0dea0}}, 0x2, 0x0}, - {0x00,(0x0a << 3)|0x0, {{0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0x0dea0}}, 0x3, 0x0}, - {0x00,(0x0b << 3)|0x0, {{0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0x0dea0}}, 0x4, 0x0}, - {0x00,(0x0c << 3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x5, 0x0}, - {0x00,(0x0d << 3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x6, 0x0}, - {0x00,(0x11 << 3)|0x0, {{0x00, 0xdea0}, {0x00, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, - {0x00,(0x0f << 3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, - {0x00,(0x01 << 3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, - {0x00,(0x10 << 3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, - {0x00,(0x12 << 3)|0x0, {{0x01, 0xdea0}, {0x00, 0xdea0}, {0x00, 0xdea0}, {0x00, 0x0dea0}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/asus/mew-vm/romstage.c b/src/mainboard/asus/mew-vm/romstage.c deleted file mode 100644 index 947003992a..0000000000 --- a/src/mainboard/asus/mew-vm/romstage.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <stdlib.h> -#include <console/console.h> -#include <superio/smsc/lpc47b272/lpc47b272.h> -#include <northbridge/intel/i82810/raminit.h> -#include <cpu/x86/bist.h> -#include <cpu/intel/romstage.h> -#include <southbridge/intel/i82801ax/i82801ax.h> -#include <lib.h> - -#define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1) - -void mainboard_romstage_entry(unsigned long bist) -{ - lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - enable_smbus(); - report_bist_failure(bist); - dump_spd_registers(); - sdram_set_registers(); - sdram_set_spd_registers(); - sdram_enable(); -} diff --git a/src/mainboard/ecs/Kconfig b/src/mainboard/ecs/Kconfig deleted file mode 100644 index c570ce2bce..0000000000 --- a/src/mainboard/ecs/Kconfig +++ /dev/null @@ -1,31 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if VENDOR_ECS - -choice - prompt "Mainboard model" - -source "src/mainboard/ecs/*/Kconfig.name" - -endchoice - -source "src/mainboard/ecs/*/Kconfig" - -config MAINBOARD_VENDOR - string - default "ECS" - -endif # VENDOR_ECS diff --git a/src/mainboard/ecs/Kconfig.name b/src/mainboard/ecs/Kconfig.name deleted file mode 100644 index 778c3691b2..0000000000 --- a/src/mainboard/ecs/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config VENDOR_ECS - bool "ECS" diff --git a/src/mainboard/ecs/p6iwp-fe/Kconfig b/src/mainboard/ecs/p6iwp-fe/Kconfig deleted file mode 100644 index 9afae9a039..0000000000 --- a/src/mainboard/ecs/p6iwp-fe/Kconfig +++ /dev/null @@ -1,39 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Anders Jenbo <anders@jenbo.dk> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_ECS_P6IWP_FE - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_INTEL_SOCKET_PGA370 - select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801AX - select SUPERIO_ITE_IT8712F - select HAVE_PIRQ_TABLE - select BOARD_ROMSIZE_KB_512 - -config MAINBOARD_DIR - string - default ecs/p6iwp-fe - -config MAINBOARD_PART_NUMBER - string - default "P6IWP-FE" - -config IRQ_SLOT_COUNT - int - default 10 - -endif # BOARD_ECS_P6IWP_FE diff --git a/src/mainboard/ecs/p6iwp-fe/Kconfig.name b/src/mainboard/ecs/p6iwp-fe/Kconfig.name deleted file mode 100644 index 66fc8c3241..0000000000 --- a/src/mainboard/ecs/p6iwp-fe/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ECS_P6IWP_FE - bool "P6IWP-Fe" diff --git a/src/mainboard/ecs/p6iwp-fe/board_info.txt b/src/mainboard/ecs/p6iwp-fe/board_info.txt deleted file mode 100644 index 31ce6e4154..0000000000 --- a/src/mainboard/ecs/p6iwp-fe/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Category: desktop -Board URL: http://www.ecs.com.tw/ECSWebSite/Product/Product_Detail.aspx?CategoryID=1&DetailID=95&DetailName=Feature&MenuID=24&LanID=4 -ROM package: PLCC -ROM protocol: FWH -ROM socketed: y -Flashrom support: y diff --git a/src/mainboard/ecs/p6iwp-fe/devicetree.cb b/src/mainboard/ecs/p6iwp-fe/devicetree.cb deleted file mode 100644 index 9c36a20285..0000000000 --- a/src/mainboard/ecs/p6iwp-fe/devicetree.cb +++ /dev/null @@ -1,82 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Anders Jenbo <anders@jenbo.dk> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip northbridge/intel/i82810 # Northbridge - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # CPU - device lapic 0 on end # APIC - end - end - device domain 0 on # PCI domain - device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) - device pci 1.0 on end # Chipset Graphics Controller (CGC) - chip southbridge/intel/i82801ax # Southbridge - register "ide0_enable" = "1" - register "ide1_enable" = "1" - - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA bridge - chip superio/ite/it8712f # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # EC - io 0x60 = 0x290 - io 0x62 = 0x230 - irq 0x70 = 9 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO - io 0x62 = 0x1220 - io 0x64 = 0x1200 - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # Game port - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end - end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMBus - end - end -end diff --git a/src/mainboard/ecs/p6iwp-fe/irq_tables.c b/src/mainboard/ecs/p6iwp-fe/irq_tables.c deleted file mode 100644 index 23ffbb156e..0000000000 --- a/src/mainboard/ecs/p6iwp-fe/irq_tables.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Anders Jenbo <anders@jenbo.dk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x1f << 3) | 0x0, /* Interrupt router dev */ - 0x1c00, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x7000, /* Device */ - 0, /* Miniport */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x7, /* Checksum (has to be set to some value that - * would give 0 after the sum of all bytes - * for this structure (including checksum). - */ - { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x1e << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x1, 0x0}, - {0x00, (0x10 << 3) | 0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x2, 0x0}, - {0x01, (0x04 << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x3, 0x0}, - {0x01, (0x05 << 3) | 0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x4, 0x0}, - {0x01, (0x0a << 3) | 0x0, {{0x63, 0xdeb8}, {0x62, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x5, 0x0}, - {0x01, (0x07 << 3) | 0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x6, 0x0}, - {0x01, (0x08 << 3) | 0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x7, 0x0}, - {0x01, (0x09 << 3) | 0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x8, 0x0}, - {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x0, 0x0}, - {0x00, (0x1f << 3) | 0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/ecs/p6iwp-fe/romstage.c b/src/mainboard/ecs/p6iwp-fe/romstage.c deleted file mode 100644 index f092e1483e..0000000000 --- a/src/mainboard/ecs/p6iwp-fe/romstage.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> - * Copyright (C) 2010 Anders Jenbo <anders@jenbo.dk> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stdlib.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <console/console.h> -#include <southbridge/intel/i82801ax/i82801ax.h> -#include <northbridge/intel/i82810/raminit.h> -#include <cpu/x86/bist.h> -#include <cpu/intel/romstage.h> -#include <superio/ite/common/ite.h> -#include <superio/ite/it8712f/it8712f.h> -#include <lib.h> - -#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) -#define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO) - -void mainboard_romstage_entry(unsigned long bist) -{ - ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - report_bist_failure(bist); - enable_smbus(); - dump_spd_registers(); - sdram_set_registers(); - sdram_set_spd_registers(); - sdram_enable(); - dump_spd_registers(); -} diff --git a/src/mainboard/hp/e_vectra_p2706t/Kconfig b/src/mainboard/hp/e_vectra_p2706t/Kconfig deleted file mode 100644 index 28594f019d..0000000000 --- a/src/mainboard/hp/e_vectra_p2706t/Kconfig +++ /dev/null @@ -1,42 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# FIXME: It's a PC87360 actually. -# FIXME: It's an i810E actually! -# FIXME: ROM chip size really 512KB? -if BOARD_HP_E_VECTRA_P2706T - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_INTEL_SOCKET_PGA370 - select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801AX - select SUPERIO_NSC_PC87360 - select HAVE_PIRQ_TABLE - select BOARD_ROMSIZE_KB_512 - -config MAINBOARD_DIR - string - default hp/e_vectra_p2706t - -config MAINBOARD_PART_NUMBER - string - default "e-Vectra P2706T" - -config IRQ_SLOT_COUNT - int - default 3 - -endif # BOARD_HP_E_VECTRA_P2706T diff --git a/src/mainboard/hp/e_vectra_p2706t/Kconfig.name b/src/mainboard/hp/e_vectra_p2706t/Kconfig.name deleted file mode 100644 index f37ab1ef0c..0000000000 --- a/src/mainboard/hp/e_vectra_p2706t/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_HP_E_VECTRA_P2706T - bool "e-Vectra P2706T" diff --git a/src/mainboard/hp/e_vectra_p2706t/board_info.txt b/src/mainboard/hp/e_vectra_p2706t/board_info.txt deleted file mode 100644 index 4df7a1ec9d..0000000000 --- a/src/mainboard/hp/e_vectra_p2706t/board_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -Category: desktop -Release year: 2000 diff --git a/src/mainboard/hp/e_vectra_p2706t/devicetree.cb b/src/mainboard/hp/e_vectra_p2706t/devicetree.cb deleted file mode 100644 index 04d6d8d689..0000000000 --- a/src/mainboard/hp/e_vectra_p2706t/devicetree.cb +++ /dev/null @@ -1,58 +0,0 @@ -# TODO: i810E actually! -chip northbridge/intel/i82810 # Northbridge - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # CPU - device lapic 0 on end # APIC - end - end - device domain 0 on - device pci 0.0 on end # Host bridge - device pci 1.0 on end # Onboard VGA - chip southbridge/intel/i82801ax # Southbridge - register "ide0_enable" = "1" - register "ide1_enable" = "1" - - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA/LPC bridge - # TODO: PC87364 actually! - # TODO: Check Super I/O settings and compare to superiotool -d. - chip superio/nsc/pc87360 # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 off end # SWC - device pnp 2e.5 off end # PS/2 mouse - device pnp 2e.6 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end # ACB - device pnp 2e.9 off end # FSCM - device pnp 2e.a off end # WDT - end - end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMBus - device pci 1f.5 on end # AC'97 audio - device pci 1f.6 off end # AC'97 modem (N/A ?) - end - end -end diff --git a/src/mainboard/hp/e_vectra_p2706t/irq_tables.c b/src/mainboard/hp/e_vectra_p2706t/irq_tables.c deleted file mode 100644 index 18e2c504fc..0000000000 --- a/src/mainboard/hp/e_vectra_p2706t/irq_tables.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, - PIRQ_VERSION, - 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x1f << 3) | 0x0, /* Interrupt router device */ - 0x0, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x2410, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x59, /* Checksum */ - { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}}, 0x0, 0x0}, - {0x00, (0x1e << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x0, 0x0}, - {0x00, (0x1f << 3) | 0x0, {{0xfe, 0x4000}, {0x61, 0xdeb8}, {0x00, 0x0000}, {0x63, 0xdeb8}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/hp/e_vectra_p2706t/romstage.c b/src/mainboard/hp/e_vectra_p2706t/romstage.c deleted file mode 100644 index 1d3c3fd5c2..0000000000 --- a/src/mainboard/hp/e_vectra_p2706t/romstage.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <stdlib.h> -#include <console/console.h> -/* TODO: It's a PC87364 actually! */ -#include <superio/nsc/pc87360/pc87360.h> -/* TODO: It's i810E actually! */ -#include <northbridge/intel/i82810/raminit.h> -#include <cpu/x86/bist.h> -#include <cpu/intel/romstage.h> -#include <southbridge/intel/i82801ax/i82801ax.h> -#include <lib.h> - -/* TODO: It's a PC87364 actually! */ -#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1) - -void mainboard_romstage_entry(unsigned long bist) -{ - /* TODO: It's a PC87364 actually! */ - pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - enable_smbus(); - report_bist_failure(bist); - dump_spd_registers(); - sdram_set_registers(); - sdram_set_spd_registers(); - sdram_enable(); -} diff --git a/src/mainboard/intel/d810e2cb/Kconfig b/src/mainboard/intel/d810e2cb/Kconfig deleted file mode 100644 index 8695da962c..0000000000 --- a/src/mainboard/intel/d810e2cb/Kconfig +++ /dev/null @@ -1,39 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Joseph Smith <joe@settoplinux.org> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_INTEL_D810E2CB - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_INTEL_SOCKET_FC_PGA370 - select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801BX - select SUPERIO_SMSC_SMSCSUPERIO - select HAVE_PIRQ_TABLE - select USE_WATCHDOG_ON_BOOT - select BOARD_ROMSIZE_KB_512 - -config MAINBOARD_DIR - string - default intel/d810e2cb - -config MAINBOARD_PART_NUMBER - string - default "D810E2CB" - -config IRQ_SLOT_COUNT - int - default 7 - -endif # BOARD_INTEL_D810E2CB diff --git a/src/mainboard/intel/d810e2cb/Kconfig.name b/src/mainboard/intel/d810e2cb/Kconfig.name deleted file mode 100644 index 8bf8624ab8..0000000000 --- a/src/mainboard/intel/d810e2cb/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_INTEL_D810E2CB - bool "D810E2CB" diff --git a/src/mainboard/intel/d810e2cb/board_info.txt b/src/mainboard/intel/d810e2cb/board_info.txt deleted file mode 100644 index cc1327cd82..0000000000 --- a/src/mainboard/intel/d810e2cb/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Category: desktop -Board URL: http://downloadcenter.intel.com/Detail_Desc.aspx?agr=Y&DwnldID=17789&lang=eng&wapkw=d810e2cb -ROM package: PLCC -ROM protocol: FWH -ROM socketed: n -Release year: 1999 diff --git a/src/mainboard/intel/d810e2cb/devicetree.cb b/src/mainboard/intel/d810e2cb/devicetree.cb deleted file mode 100644 index 461a357a40..0000000000 --- a/src/mainboard/intel/d810e2cb/devicetree.cb +++ /dev/null @@ -1,78 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Joseph Smith <joe@settoplinux.org> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip northbridge/intel/i82810 # Northbridge - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_FC_PGA370 # CPU - device lapic 0 on end # APIC - end - end - device domain 0 on # PCI domain - device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) - device pci 1.0 on end # Chipset Graphics Controller (CGC) - chip southbridge/intel/i82801bx # Southbridge - register "pirqa_routing" = "0x05" - register "pirqb_routing" = "0x06" - register "pirqc_routing" = "0x07" - register "pirqd_routing" = "0x09" - register "pirqe_routing" = "0x0a" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x0b" - - register "ide0_enable" = "1" - register "ide1_enable" = "1" - - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA bridge - chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47M102) - device pnp 4e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 4 - end - device pnp 4e.4 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.5 off end # COM2 - device pnp 4e.7 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 4e.9 off end # Game port - device pnp 4e.a on # Runtime registers - io 0x60 = 0x800 - end - device pnp 4e.b off end # MPU-401 - end - end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMbus - device pci 1f.4 on end # USB - device pci 1f.5 on end # Audio controller - device pci 1f.6 off end # Modem controller - end - end -end diff --git a/src/mainboard/intel/d810e2cb/gpio.c b/src/mainboard/intel/d810e2cb/gpio.c deleted file mode 100644 index 84e49d69a6..0000000000 --- a/src/mainboard/intel/d810e2cb/gpio.c +++ /dev/null @@ -1,209 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Joseph Smith <joe@settoplinux.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <delay.h> - -#define PME_DEV PNP_DEV(0x4e, 0x0a) -#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */ - -/* Early mainboard specific GPIO setup. */ -static void mb_gpio_init(void) -{ - device_t dev; - uint16_t port; - - /* Southbridge GPIOs. */ - /* Set the LPC device statically. */ - dev = PCI_DEV(0x0, 0x1f, 0x0); - - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1)); - pci_write_config8(dev, GPIO_CNTL, 0x10); - - udelay(10); - outl(0x1a203180, GPIO_BASE_ADDR + 0x00); /* GPIO_USE_SEL */ - outl(0x0000ffff, GPIO_BASE_ADDR + 0x04); /* GP_IO_SEL */ - outl(0x13bf0000, GPIO_BASE_ADDR + 0x0c); /* GP_LVL */ - outl(0x00040000, GPIO_BASE_ADDR + 0x18); /* GPO_BLINK */ - outl(0x000039ff, GPIO_BASE_ADDR + 0x2c); /* GPI_INV */ - - /* Super I/O GPIOs. */ - dev = PME_DEV; - port = dev >> 8; - - /* Enter the configuration state. */ - outb(0x55, port); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR); - pnp_set_enable(dev, 1); - - /* GP10 - J1B1 */ - outl(0x01, PME_IO_BASE_ADDR + 0x23); - - /* GP11 - J1B2 */ - outl(0x01, PME_IO_BASE_ADDR + 0x24); - - /* GP12 - J2B1 */ - outl(0x01, PME_IO_BASE_ADDR + 0x25); - - /* GP13 - J2B2 */ - outl(0x01, PME_IO_BASE_ADDR + 0x26); - - /* GP14 - J1X */ - outl(0x01, PME_IO_BASE_ADDR + 0x27); - - /* GP15 - J1Y */ - outl(0x01, PME_IO_BASE_ADDR + 0x28); - - /* GP16 - J2X */ - outl(0x01, PME_IO_BASE_ADDR + 0x29); - - /* GP17 - J2Y */ - outl(0x01, PME_IO_BASE_ADDR + 0x2a); - - /* GP20 - 8042 P17 */ - outl(0x01, PME_IO_BASE_ADDR + 0x2b); - - /* GP21 - 8042 P16 */ - outl(0x00, PME_IO_BASE_ADDR + 0x2c); - - /* GP22 - 8042 P12 */ - outl(0x00, PME_IO_BASE_ADDR + 0x2d); - - /* GP24 */ - outl(0x00, PME_IO_BASE_ADDR + 0x2f); - - /* GP25 - MIDI_IN */ - outl(0x01, PME_IO_BASE_ADDR + 0x30); - - /* GP26 - MIDI_OUT */ - outl(0x01, PME_IO_BASE_ADDR + 0x31); - - /* GP27 - nIO_SMI */ - outl(0x04, PME_IO_BASE_ADDR + 0x32); - - /* GP30 - FAN_TACH2 */ - outl(0x05, PME_IO_BASE_ADDR + 0x33); - - /* GP31 - FAN_TACH1 */ - outl(0x05, PME_IO_BASE_ADDR + 0x34); - - /* GP32 - FAN2 */ - outl(0x04, PME_IO_BASE_ADDR + 0x35); - - /* GP33 - FAN1 */ - outl(0x04, PME_IO_BASE_ADDR + 0x36); - - /* GP34 - IRRX2 */ - outl(0x05, PME_IO_BASE_ADDR + 0x37); - - /* GP35 - IRTX2 */ - outl(0x04, PME_IO_BASE_ADDR + 0x38); - - /* GP36 - nKBDRST */ - outl(0x84, PME_IO_BASE_ADDR + 0x39); - - /* GP37 - A20M */ - outl(0x84, PME_IO_BASE_ADDR + 0x3a); - - /* GP40 - DRVDEN0 */ - outl(0x04, PME_IO_BASE_ADDR + 0x3b); - - /* GP41 - DRVDEN1 */ - outl(0x04, PME_IO_BASE_ADDR + 0x3c); - - /* GP42 - nIO_PME */ - outl(0x84, PME_IO_BASE_ADDR + 0x3d); - - /* GP43 */ - outl(0x00, PME_IO_BASE_ADDR + 0x3e); - - /* GP50 - nIR2 */ - outl(0x05, PME_IO_BASE_ADDR + 0x3f); - - /* GP51 - nDCD2 */ - outl(0x05, PME_IO_BASE_ADDR + 0x40); - - /* GP52 - RXD2 */ - outl(0x05, PME_IO_BASE_ADDR + 0x41); - - /* GP53 - TXD2 */ - outl(0x04, PME_IO_BASE_ADDR + 0x42); - - /* GP54 - nDSR2 */ - outl(0x05, PME_IO_BASE_ADDR + 0x43); - - /* GP55 - nRTS2 */ - outl(0x04, PME_IO_BASE_ADDR + 0x44); - - /* GP56 - nCTS2 */ - outl(0x05, PME_IO_BASE_ADDR + 0x45); - - /* GP57 - nDTR2 */ - outl(0x04, PME_IO_BASE_ADDR + 0x46); - - /* GP60 - LED1 */ - outl(0x84, PME_IO_BASE_ADDR + 0x47); - - /* GP61 - LED2 */ - outl(0x84, PME_IO_BASE_ADDR + 0x48); - - /* GP1 */ - outl(0x00, PME_IO_BASE_ADDR + 0x4b); - - /* GP2 */ - outl(0x14, PME_IO_BASE_ADDR + 0x4c); - - /* GP3 */ - outl(0xda, PME_IO_BASE_ADDR + 0x4d); - - /* GP4 */ - outl(0x08, PME_IO_BASE_ADDR + 0x4e); - - /* GP5 */ - outl(0x00, PME_IO_BASE_ADDR + 0x4f); - - /* GP6 */ - outl(0x00, PME_IO_BASE_ADDR + 0x50); - - /* FAN1 */ - outl(0x01, PME_IO_BASE_ADDR + 0x56); - - /* FAN2 */ - outl(0x01, PME_IO_BASE_ADDR + 0x57); - - /* Fan Control */ - outl(0xf0, PME_IO_BASE_ADDR + 0x58); - - /* Fan1 Preload */ - outl(0x00, PME_IO_BASE_ADDR + 0x5b); - - /* Fan2 Preload */ - outl(0x00, PME_IO_BASE_ADDR + 0x5c); - - /* LED1 */ - outl(0x03, PME_IO_BASE_ADDR + 0x5d); - - /* LED2 */ - outl(0x03, PME_IO_BASE_ADDR + 0x5e); - - /* Keyboard Scan Code */ - outl(0x00, PME_IO_BASE_ADDR + 0x5f); - - /* Exit the configuration state. */ - outb(0xaa, port); -} diff --git a/src/mainboard/intel/d810e2cb/irq_tables.c b/src/mainboard/intel/d810e2cb/irq_tables.c deleted file mode 100644 index 7d4de66c1e..0000000000 --- a/src/mainboard/intel/d810e2cb/irq_tables.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Joseph Smith <joe@settoplinux.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus (7)*/ - 0x00, /* Interrupt router bus */ - (0x1f << 3) | 0x0, /* Interrupt router dev */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x2440, /* Device */ - 0, /* Miniport */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xd9, /* Checksum (has to be set to some value that - * would give 0 after the sum of all bytes - * for this structure (including checksum). - */ - { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x00 << 3) | 0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdeb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x1e << 3) | 0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x00, (0x1f << 3) | 0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x6b, 0xdef8}, {0x63, 0xdef8}}, 0x0, 0x0}, - {0x01, (0x01 << 3) | 0x0, {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}}, 0x1, 0x0}, - {0x01, (0x02 << 3) | 0x0, {{0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}}, 0x2, 0x0}, - {0x01, (0x08 << 3) | 0x0, {{0x68, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/intel/d810e2cb/romstage.c b/src/mainboard/intel/d810e2cb/romstage.c deleted file mode 100644 index 5bcee0c544..0000000000 --- a/src/mainboard/intel/d810e2cb/romstage.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Joseph Smith <joe@settoplinux.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stdlib.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <console/console.h> -#include <southbridge/intel/i82801bx/i82801bx.h> -#include <northbridge/intel/i82810/raminit.h> -#include <cpu/x86/bist.h> -#include <cpu/intel/romstage.h> -#include <superio/smsc/smscsuperio/smscsuperio.h> -#include "gpio.c" -#include <lib.h> - -#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) - -void mainboard_romstage_entry(unsigned long bist) -{ - /* Set southbridge and Super I/O GPIOs. */ - mb_gpio_init(); - - smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - report_bist_failure(bist); - enable_smbus(); - dump_spd_registers(); - sdram_set_registers(); - sdram_set_spd_registers(); - sdram_enable(); -} diff --git a/src/mainboard/mitac/6513wu/Kconfig b/src/mainboard/mitac/6513wu/Kconfig deleted file mode 100644 index 0266016aad..0000000000 --- a/src/mainboard/mitac/6513wu/Kconfig +++ /dev/null @@ -1,38 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_MITAC_6513WU - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_INTEL_SOCKET_PGA370 - select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801AX - select SUPERIO_SMSC_SMSCSUPERIO - select HAVE_PIRQ_TABLE - select BOARD_ROMSIZE_KB_512 - -config MAINBOARD_DIR - string - default mitac/6513wu - -config MAINBOARD_PART_NUMBER - string - default "6513WU" - -config IRQ_SLOT_COUNT - int - default 8 - -endif # BOARD_MITAC_6513WU diff --git a/src/mainboard/mitac/6513wu/Kconfig.name b/src/mainboard/mitac/6513wu/Kconfig.name deleted file mode 100644 index bee249ac20..0000000000 --- a/src/mainboard/mitac/6513wu/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_MITAC_6513WU - bool "6513WU" diff --git a/src/mainboard/mitac/6513wu/board_info.txt b/src/mainboard/mitac/6513wu/board_info.txt deleted file mode 100644 index 3364212a51..0000000000 --- a/src/mainboard/mitac/6513wu/board_info.txt +++ /dev/null @@ -1,4 +0,0 @@ -Category: desktop -Board URL: http://web.archive.org/web/20050313054828/http://www.mitac.com/micweb/products/tyan/6513wu/6513wu.htm -ROM package: PLCC -Flashrom support: y diff --git a/src/mainboard/mitac/6513wu/devicetree.cb b/src/mainboard/mitac/6513wu/devicetree.cb deleted file mode 100644 index 8d99df7239..0000000000 --- a/src/mainboard/mitac/6513wu/devicetree.cb +++ /dev/null @@ -1,80 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Michael Gold <mgold@ncf.ca> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip northbridge/intel/i82810 # Northbridge - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # CPU - device lapic 0 on end # APIC - end - end - device domain 0 on # PCI domain - device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) - device pci 1.0 on end - chip southbridge/intel/i82801ax # Southbridge - register "pirqa_routing" = "0x03" - register "pirqb_routing" = "0x05" - register "pirqc_routing" = "0x09" - register "pirqd_routing" = "0x0b" - - register "ide0_enable" = "1" - register "ide1_enable" = "1" - - device pci 1e.0 on # PCI bridge - device pci 5.0 on end # Audio controller (ESS ES1988) - end - device pci 1f.0 on # ISA bridge - chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47U332) - device pnp 4e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 4e.4 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.5 on # MIDI port (MPU-401) - io 0x60 = 0x330 - irq 0x70 = 10 - end - device pnp 4e.7 on # PS/2 keyboard / mouse - io 0x60 = 0x60 # XXX: not relocatable - io 0x62 = 0x64 # XXX: not relocatable - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 4e.9 on # Game port - io 0x60 = 0x201 - end - device pnp 4e.a on # Runtime registers - io 0x60 = 0x400 - end - device pnp 4e.b off end # SMBus - end - end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMbus - device pci 1f.5 off end # Audio controller - device pci 1f.6 off end # Modem - end - end -end diff --git a/src/mainboard/mitac/6513wu/irq_tables.c b/src/mainboard/mitac/6513wu/irq_tables.c deleted file mode 100644 index 52979bb3bf..0000000000 --- a/src/mainboard/mitac/6513wu/irq_tables.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Michael Gold <mgold@ncf.ca> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/pirq_routing.h> - -/* - * Each of PIRQA..D can be routed to IRQ 3-7, 9-12, 14, or 15; but the - * selected IRQs can't be shared with ISA devices (Intel DS 290655-003, - * section 5.7.6). - * - * Correspondingly, the IRQs used on the Super I/O (4,6,7,10,12) are - * excluded from the masks, leaving 0xca28 (3,5,9,11,14,15). - */ - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x1f << 3) | 0x0, /* Interrupt router dev */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x7000, /* Device */ - 0, /* Miniport */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xb6, /* Checksum (has to be set to some value that - * would give 0 after the sum of all bytes - * for this structure (including checksum). - */ - { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x1f << 3) | 0x0, {{0x00, 0x0000}, {0x61, 0xca28}, {0x00, 0x0000}, {0x63, 0xca28}}, 0x0, 0x0}, - {0x00, (0x1e << 3) | 0x0, {{0x60, 0xca28}, {0x61, 0xca28}, {0x62, 0xca28}, {0x63, 0xca28}}, 0x0, 0x0}, - {0x00, (0x01 << 3) | 0x0, {{0x60, 0xca28}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x01, (0x05 << 3) | 0x0, {{0x63, 0xca28}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, - {0x01, (0x08 << 3) | 0x0, {{0x60, 0xca28}, {0x61, 0xca28}, {0x62, 0xca28}, {0x63, 0xca28}}, 0x1, 0x0}, - {0x01, (0x09 << 3) | 0x0, {{0x61, 0xca28}, {0x62, 0xca28}, {0x63, 0xca28}, {0x60, 0xca28}}, 0x2, 0x0}, - {0x01, (0x0a << 3) | 0x0, {{0x62, 0xca28}, {0x63, 0xca28}, {0x60, 0xca28}, {0x61, 0xca28}}, 0x3, 0x0}, - {0x01, (0x0b << 3) | 0x0, {{0x63, 0xca28}, {0x60, 0xca28}, {0x61, 0xca28}, {0x62, 0xca28}}, 0x4, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/mitac/6513wu/romstage.c b/src/mainboard/mitac/6513wu/romstage.c deleted file mode 100644 index 66989d9f20..0000000000 --- a/src/mainboard/mitac/6513wu/romstage.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Michael Gold <mgold@ncf.ca> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stdlib.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <console/console.h> -#include <southbridge/intel/i82801ax/i82801ax.h> -#include <northbridge/intel/i82810/raminit.h> -#include <delay.h> -#include <cpu/x86/bist.h> -#include <cpu/intel/romstage.h> -#include <superio/smsc/smscsuperio/smscsuperio.h> -#include <lib.h> - -#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) - -void mainboard_romstage_entry(unsigned long bist) -{ - smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - report_bist_failure(bist); - enable_smbus(); - dump_spd_registers(); - sdram_set_registers(); - sdram_set_spd_registers(); - sdram_enable(); -} diff --git a/src/mainboard/mitac/Kconfig b/src/mainboard/mitac/Kconfig deleted file mode 100644 index aca84bc855..0000000000 --- a/src/mainboard/mitac/Kconfig +++ /dev/null @@ -1,30 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if VENDOR_MITAC - -choice - prompt "Mainboard model" - -source "src/mainboard/mitac/*/Kconfig.name" - -endchoice - -source "src/mainboard/mitac/*/Kconfig" - -config MAINBOARD_VENDOR - string - default "Mitac" - -endif # VENDOR_MITAC diff --git a/src/mainboard/mitac/Kconfig.name b/src/mainboard/mitac/Kconfig.name deleted file mode 100644 index f9c1c4bbc6..0000000000 --- a/src/mainboard/mitac/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config VENDOR_MITAC - bool "Mitac" diff --git a/src/mainboard/msi/ms6178/Kconfig b/src/mainboard/msi/ms6178/Kconfig deleted file mode 100644 index c7bd464a3c..0000000000 --- a/src/mainboard/msi/ms6178/Kconfig +++ /dev/null @@ -1,43 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_MSI_MS_6178 - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_INTEL_SOCKET_PGA370 - select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801AX - select SUPERIO_WINBOND_W83627HF - select HAVE_PIRQ_TABLE - select BOARD_ROMSIZE_KB_512 - -config MAINBOARD_DIR - string - default msi/ms6178 - -config MAINBOARD_PART_NUMBER - string - default "MS-6178" - -config IRQ_SLOT_COUNT - int - default 4 - -# No need to override the chipset VGA_BIOS_ID. -config VGA_BIOS_FILE - string - default "i810.vga" - -endif # BOARD_MSI_MS_6178 diff --git a/src/mainboard/msi/ms6178/Kconfig.name b/src/mainboard/msi/ms6178/Kconfig.name deleted file mode 100644 index fbd0fc11a4..0000000000 --- a/src/mainboard/msi/ms6178/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_MSI_MS_6178 - bool "MS-6178" diff --git a/src/mainboard/msi/ms6178/board_info.txt b/src/mainboard/msi/ms6178/board_info.txt deleted file mode 100644 index bd5f6f7cf6..0000000000 --- a/src/mainboard/msi/ms6178/board_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -Category: desktop -Board URL: http://no.msi.com/product/mb/MS-6178.html -ROM package: PLCC -ROM socketed: y -Release year: 1999 diff --git a/src/mainboard/msi/ms6178/devicetree.cb b/src/mainboard/msi/ms6178/devicetree.cb deleted file mode 100644 index 12703f5a8b..0000000000 --- a/src/mainboard/msi/ms6178/devicetree.cb +++ /dev/null @@ -1,79 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip northbridge/intel/i82810 # Northbridge - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # CPU - device lapic 0 on end # APIC - end - end - device domain 0 on - device pci 0.0 on end # Host bridge - device pci 1.0 on end # Onboard VGA - chip southbridge/intel/i82801ax # Southbridge - register "ide0_enable" = "1" - register "ide1_enable" = "1" - - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA/LPC bridge - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 (only header on board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard/mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # Keyboard interrupt - irq 0x72 = 12 # Mouse interrupt - end - device pnp 2e.6 off end # Consumer IR (TODO) - device pnp 2e.7 on # Game port / MIDI / GPIO 1 - io 0x60 = 0x201 - io 0x62 = 0x330 - irq 0x70 = 9 - end - device pnp 2e.8 on end # GPIO 2 - device pnp 2e.9 on end # GPIO 3 - device pnp 2e.a on end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMBus - device pci 1f.5 on end # AC'97 audio - device pci 1f.6 on end # AC'97 modem - end - end -end diff --git a/src/mainboard/msi/ms6178/irq_tables.c b/src/mainboard/msi/ms6178/irq_tables.c deleted file mode 100644 index fae5bcf998..0000000000 --- a/src/mainboard/msi/ms6178/irq_tables.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, - PIRQ_VERSION, - 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x1f << 3) | 0x0, /* Interrupt router device */ - 0x1c00, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x7000, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x1a, /* Checksum */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x1e << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, - {0x00,(0x10 << 3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, - {0x00,(0x01 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, - {0x00,(0x1f << 3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c deleted file mode 100644 index 2f1180e96f..0000000000 --- a/src/mainboard/msi/ms6178/romstage.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <stdlib.h> -#include <console/console.h> -#include <superio/winbond/common/winbond.h> -#include <superio/winbond/w83627hf/w83627hf.h> -#include <northbridge/intel/i82810/raminit.h> -#include <cpu/x86/bist.h> -#include <cpu/intel/romstage.h> -#include <southbridge/intel/i82801ax/i82801ax.h> -#include <lib.h> - -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -#define DUMMY_DEV PNP_DEV(0x2e, 0) - -void mainboard_romstage_entry(unsigned long bist) -{ - winbond_set_clksel_48(DUMMY_DEV); - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - enable_smbus(); - report_bist_failure(bist); - dump_spd_registers(); - sdram_set_registers(); - sdram_set_spd_registers(); - sdram_enable(); -} diff --git a/src/mainboard/nec/Kconfig b/src/mainboard/nec/Kconfig deleted file mode 100644 index f2907356a1..0000000000 --- a/src/mainboard/nec/Kconfig +++ /dev/null @@ -1,30 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if VENDOR_NEC - -choice - prompt "Mainboard model" - -source "src/mainboard/nec/*/Kconfig.name" - -endchoice - -source "src/mainboard/nec/*/Kconfig" - -config MAINBOARD_VENDOR - string - default "NEC" - -endif # VENDOR_NEC diff --git a/src/mainboard/nec/Kconfig.name b/src/mainboard/nec/Kconfig.name deleted file mode 100644 index 5f4f89212c..0000000000 --- a/src/mainboard/nec/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config VENDOR_NEC - bool "NEC" diff --git a/src/mainboard/nec/powermate2000/Kconfig b/src/mainboard/nec/powermate2000/Kconfig deleted file mode 100644 index fe546faca4..0000000000 --- a/src/mainboard/nec/powermate2000/Kconfig +++ /dev/null @@ -1,38 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_NEC_POWERMATE_2000 - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_INTEL_SOCKET_PGA370 - select NORTHBRIDGE_INTEL_I82810 - select SOUTHBRIDGE_INTEL_I82801AX - select SUPERIO_SMSC_SMSCSUPERIO - select HAVE_PIRQ_TABLE - select BOARD_ROMSIZE_KB_512 - -config MAINBOARD_DIR - string - default nec/powermate2000 - -config MAINBOARD_PART_NUMBER - string - default "PowerMate 2000" - -config IRQ_SLOT_COUNT - int - default 5 - -endif # BOARD_NEC_POWERMATE_2000 diff --git a/src/mainboard/nec/powermate2000/Kconfig.name b/src/mainboard/nec/powermate2000/Kconfig.name deleted file mode 100644 index 3f46dceba2..0000000000 --- a/src/mainboard/nec/powermate2000/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_NEC_POWERMATE_2000 - bool "PowerMate 2000" diff --git a/src/mainboard/nec/powermate2000/board_info.txt b/src/mainboard/nec/powermate2000/board_info.txt deleted file mode 100644 index 50a4b2a6d9..0000000000 --- a/src/mainboard/nec/powermate2000/board_info.txt +++ /dev/null @@ -1,4 +0,0 @@ -Category: desktop -Board URL: http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/ -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/nec/powermate2000/devicetree.cb b/src/mainboard/nec/powermate2000/devicetree.cb deleted file mode 100644 index a3f164e968..0000000000 --- a/src/mainboard/nec/powermate2000/devicetree.cb +++ /dev/null @@ -1,53 +0,0 @@ -chip northbridge/intel/i82810 # Northbridge - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # CPU - device lapic 0 on end # APIC - end - end - device domain 0 on - device pci 0.0 on end # Host bridge - device pci 1.0 off end # Onboard video - chip southbridge/intel/i82801ax # Southbridge - register "ide0_enable" = "1" - register "ide1_enable" = "1" - - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA/LPC bridge - chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47B27x) - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 off end # Com2 (N/A) - device pnp 2e.7 on # PS/2 keyboard - irq 0x70 = 1 - irq 0x72 = 0 - end - device pnp 2e.9 off end # Game port (N/A) - device pnp 2e.a on # Power-management events (PME) - io 0x60 = 0x800 - end - device pnp 2e.b on # MIDI port - io 0x60 = 0x330 - irq 0x70 = 5 - end - end - end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMBus - device pci 1f.5 on end # AC'97 audio - device pci 1f.6 off end # AC'97 modem (N/A) - end - end -end diff --git a/src/mainboard/nec/powermate2000/irq_tables.c b/src/mainboard/nec/powermate2000/irq_tables.c deleted file mode 100644 index 6dde889591..0000000000 --- a/src/mainboard/nec/powermate2000/irq_tables.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, - PIRQ_VERSION, - 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x1f << 3) | 0x0, /* Interrupt router device */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x122e, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x6e, /* Checksum */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x1e << 3) | 0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x0, 0x0}, - {0x01, (0x03 << 3) | 0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, - {0x01, (0x04 << 3) | 0x0, {{0x62, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, - {0x00, (0x1f << 3) | 0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x0, 0x0}, - {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/nec/powermate2000/romstage.c b/src/mainboard/nec/powermate2000/romstage.c deleted file mode 100644 index 6e6358023f..0000000000 --- a/src/mainboard/nec/powermate2000/romstage.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <stdlib.h> -#include <console/console.h> -#include <superio/smsc/smscsuperio/smscsuperio.h> -#include <northbridge/intel/i82810/raminit.h> -#include <cpu/x86/bist.h> -#include <cpu/intel/romstage.h> -#include <southbridge/intel/i82801ax/i82801ax.h> -#include <lib.h> - -#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) - -void mainboard_romstage_entry(unsigned long bist) -{ - smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - enable_smbus(); - report_bist_failure(bist); - dump_spd_registers(); - sdram_set_registers(); - sdram_set_spd_registers(); - sdram_enable(); -} |