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authorShaunak Saha <shaunak.saha@intel.com>2016-09-09 14:50:34 -0700
committerMartin Roth <martinroth@google.com>2016-09-15 01:19:50 +0200
commit563de15b8a4aafad162352754975158222f8de6c (patch)
treee5af5a14a12cdd1f3153a259bc49bbd948274ce9 /src/mainboard
parent16e9d459a09ae5833776e29926207d43d2fc9a02 (diff)
downloadcoreboot-563de15b8a4aafad162352754975158222f8de6c.tar.xz
intel/amenia: Remove setting of GPIO_TIER1_SCI enable bit
This patch removes setting of gpio_tier1_sci_en from mainboard smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl now. BUG=chrome-os-partner:56483 TEST=System resumes from S3 on lidopen, powerbutton and USB wake. Also from S0iX system is resuming for WIFI wake. Change-Id: I066f0907a1c597e6fee09821910c59a8a90cccaa Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16565 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/intel/amenia/smihandler.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/intel/amenia/smihandler.c b/src/mainboard/intel/amenia/smihandler.c
index 05d363f876..eb5377be30 100644
--- a/src/mainboard/intel/amenia/smihandler.c
+++ b/src/mainboard/intel/amenia/smihandler.c
@@ -22,9 +22,6 @@
void mainboard_smi_sleep(u8 slp_typ)
{
- if (slp_typ == ACPI_S3)
- enable_gpe(GPIO_TIER_1_SCI);
-
if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
MAINBOARD_EC_S5_WAKE_EVENTS);