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authorTom Warren <twarren@nvidia.com>2014-08-05 15:05:19 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-03-25 22:31:53 +0100
commit5d98f51b254f665e385a875798be09451d2a47d9 (patch)
treee16cdf8bd317eefe409f3d0db6ea6c342657f3ad /src/mainboard
parent908f19a40630489cbe88b1e1c4e654dc79c59e41 (diff)
downloadcoreboot-5d98f51b254f665e385a875798be09451d2a47d9.tar.xz
rush/ryu: restore full-speed clocks to TPM I2C and EC SPI
Now that there's a working udelay() in tegra132, upclock CAM_I2C and SPI1 to the same speeds as used on Nyan. BUG=chrome-os-partner:30998 BRANCH=rush_ryu TEST=Built Rush and tested, no nack errors seen. Change-Id: If1ee6d5c711252e294818d6263732bb34b2fe6f0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 859c0d4fde2cf098cb829e96a5d6dec394bea600 Original-Change-Id: I58fd03ed3512c2498c793cfe30b0c302e4b0e3d4 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211043 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8910 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/rush/romstage.c4
-rw-r--r--src/mainboard/google/rush_ryu/romstage.c2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/rush/romstage.c b/src/mainboard/google/rush/romstage.c
index dae26efbce..b54058fd38 100644
--- a/src/mainboard/google/rush/romstage.c
+++ b/src/mainboard/google/rush/romstage.c
@@ -43,11 +43,11 @@ static void configure_clocks(void)
{
/* EC on SPI1 controller. */
clock_enable_clear_reset(0, CLK_H_SBC1, 0, 0, 0, 0);
- clock_configure_source(sbc1, CLK_M, 500);
+ clock_configure_source(sbc1, CLK_M, 3000);
/* TPM on I2C3 controller */
clock_enable_clear_reset(0, 0, CLK_U_I2C3, 0, 0, 0);
- clock_configure_i2c_scl_freq(i2c3, PLLP, 19);
+ clock_configure_i2c_scl_freq(i2c3, PLLP, 400);
}
void romstage_mainboard_init(void)
diff --git a/src/mainboard/google/rush_ryu/romstage.c b/src/mainboard/google/rush_ryu/romstage.c
index 3234252f0a..b2acb5d9aa 100644
--- a/src/mainboard/google/rush_ryu/romstage.c
+++ b/src/mainboard/google/rush_ryu/romstage.c
@@ -40,7 +40,7 @@ static void configure_clocks(void)
{
/* TPM on I2C3 */
clock_enable_clear_reset(0, 0, CLK_U_I2C3, 0, 0, 0);
- clock_configure_i2c_scl_freq(i2c3, PLLP, 19);
+ clock_configure_i2c_scl_freq(i2c3, PLLP, 400);
/* EC on I2C2 */
clock_enable_clear_reset(0, CLK_H_I2C2, 0, 0, 0, 0);