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| author | Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> | 2016-10-14 15:29:33 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-10-16 02:52:15 +0200 |
| commit | 63583f09872e26edb80fd891547d128abe4c6df9 (patch) | |
| tree | d0a1cdceb9c5f497bad2ba93d6bf6e06602d69f2 /src/mainboard | |
| parent | a247d8e53cebbd754e46f76412ed9d17df752308 (diff) | |
| download | coreboot-63583f09872e26edb80fd891547d128abe4c6df9.tar.xz | |
mainboard/google/reef: Set PL1 override to 12000mW
Reef is using APL SoC SKU's with 6W TDP max. We've done
experiments and found the energy calculation is wrong with
the current VR solution. Experiments show that SoC TDP max
(6W) can be reached when RAPL PL1 is set to 12W. Therefore,
we've inserted 12W override after reading the fused value (6W)
so that the system can reach the right performance level.
BUG=chrome-os-partner:56922
TEST=webGL performance(fps) not impacted before and after S3.
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Change-Id: I21c278e82b82d805f6925f4d9c82187825fd0aa0
Reviewed-on: https://review.coreboot.org/17029
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/reef/variants/baseboard/devicetree.cb | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 989acd9d25..f393019737 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -49,6 +49,11 @@ chip soc/intel/apollolake # Enable DPTF register "dptf_enable" = "1" + # PL1 override 12000 mW: the energy calculation is wrong with the + # current VR solution. Experiments show that SoC TDP max (6W) can + # be reached when RAPL PL1 is set to 12W. + register "tdp_pl1_override_mw" = "12000" + # Enable Audio Clock and Power gating register "hdaudio_clk_gate_enable" = "1" register "hdaudio_pwr_gate_enable" = "1" |