diff options
| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2020-02-12 11:41:23 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-24 12:30:57 +0000 |
| commit | 7225ed60351c48eee93f1e163e4d42480bc72185 (patch) | |
| tree | b2c1d7d99fd9aed4b01999c6acbbe6d921a5e964 /src/mainboard | |
| parent | 5cfe449814af7ab5cb874d5771c3b74a65ee72eb (diff) | |
| download | coreboot-7225ed60351c48eee93f1e163e4d42480bc72185.tar.xz | |
mb/google/dedede: Add USB configuration
Add USB port configuration in devicetree. Configure USB Over-Current (OC)
GPIOs.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I19f7563013c7d702d52b7f34a207a34abe308621
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 19 | ||||
| -rw-r--r-- | src/mainboard/google/dedede/variants/baseboard/gpio.c | 8 |
2 files changed, 26 insertions, 1 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 2d57a14f25..9dfd6b7536 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -19,6 +19,23 @@ chip soc/intel/tigerlake register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_H" + # USB Port Configuration + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C0 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Not Used + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Not Used + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Not Used + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type-C Port C0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type-C Port C1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A0 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A1 + register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Not Used + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Not Used + register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -95,7 +112,7 @@ chip soc/intel/tigerlake device pci 05.0 off end # IPU device pci 09.0 off end # Intel Trace Hub device pci 12.6 off end # GSPI 2 - device pci 14.0 off end # USB xHCI + device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 off end # PMC SRAM device pci 14.3 off end # CNVi wifi diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 8e4200ab9f..71ddadbf95 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -21,6 +21,14 @@ static const struct pad_config gpio_table[] = { /* A4 : ESPI_CS# */ /* A5 : ESPI_CLK */ /* A6 : ESPI_RESET_L */ + /* A12 : USB_OC1_N */ + PAD_NC(GPP_A12, NONE), + /* A13 : USB_OC2_N */ + PAD_NC(GPP_A13, NONE), + /* A14 : USB_OC3_N */ + PAD_NC(GPP_A14, NONE), + /* A18 : USB_OC0_N */ + PAD_NC(GPP_A18, NONE), /* B4 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT), |