AGESA f14: Consolidate early P-states setting

Change-Id: I3feed296b6ff9908e783c1221a8f61d9c548fef4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17564
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

10 files changed, 0 insertions, 40 deletions

diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index 151ce31e87..3e37e03f35 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -40,10 +40,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	/* all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
-	 */
-	__writemsr (0xc0010062, 0);
-
 	amd_initmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index d553c1b52f..980ff3edbc 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -46,9 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
-	__writemsr (0xc0010062, 0);
-
 	amd_initmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c
index 5ef95a0ceb..4b725c07ab 100644
--- a/src/mainboard/amd/south_station/romstage.c
+++ b/src/mainboard/amd/south_station/romstage.c
@@ -41,9 +41,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
-	__writemsr (0xc0010062, 0);
-
 	amd_initmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 6d2cad2b73..7a849e4739 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -43,9 +43,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
-	__writemsr(0xc0010062, 0);
-
 	amd_initmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
diff --git a/src/mainboard/elmex/pcm205400/romstage.c b/src/mainboard/elmex/pcm205400/romstage.c
index d553c1b52f..980ff3edbc 100644
--- a/src/mainboard/elmex/pcm205400/romstage.c
+++ b/src/mainboard/elmex/pcm205400/romstage.c
@@ -46,9 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
-	__writemsr (0xc0010062, 0);
-
 	amd_initmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c
index e6276ff04e..1335a8fe6a 100644
--- a/src/mainboard/gizmosphere/gizmo/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo/romstage.c
@@ -37,21 +37,9 @@
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/agesa/s3_resume.h>
 
-#define MSR_MTRR_VARIABLE_BASE6   0x020C
-#define MSR_MTRR_VARIABLE_MASK6   0x020D
-#define MSR_PSTATE_CONTROL        0xC0010062
-
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
-	msr_t msr;
-
-
-	/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
-	msr.lo = 0;
-	msr.hi = 0;
-	wrmsr (MSR_PSTATE_CONTROL, msr);
 
 	amd_initmmio();
 
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index ea2e11f324..5f22aaadbd 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -62,9 +62,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
-	__writemsr (0xc0010062, 0);
-
 	amd_initmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c
index 0beda771ad..ccb6b39bea 100644
--- a/src/mainboard/lippert/frontrunner-af/romstage.c
+++ b/src/mainboard/lippert/frontrunner-af/romstage.c
@@ -45,9 +45,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
-	__writemsr (0xc0010062, 0);
-
 	amd_initmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c
index 44a27ca1ee..b2590fc216 100644
--- a/src/mainboard/lippert/toucan-af/romstage.c
+++ b/src/mainboard/lippert/toucan-af/romstage.c
@@ -46,9 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
-	__writemsr (0xc0010062, 0);
-
 	amd_initmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c
index cf4f3fa370..f8e6318773 100644
--- a/src/mainboard/pcengines/apu1/romstage.c
+++ b/src/mainboard/pcengines/apu1/romstage.c
@@ -51,9 +51,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
-	__writemsr (0xc0010062, 0);
-
 	amd_initmmio();
 
 	if (!cpu_init_detectedx && boot_cpu()) {