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authorBora Guvendik <bora.guvendik@intel.com>2017-09-13 18:41:05 -0700
committerAaron Durbin <adurbin@chromium.org>2017-09-19 23:20:00 +0000
commit7f00965209c0c48a6e060d435d07f463f869d532 (patch)
tree9cc5fbbd28953d4522b7284c3df6bef92d06e713 /src/mainboard
parent67fb347668eb9aa85936daf140af72c4384cf5f5 (diff)
downloadcoreboot-7f00965209c0c48a6e060d435d07f463f869d532.tar.xz
mainboard/intel/cannonlake_rvp: Add PCI, PCIE IRQs to DSDT table
Change-Id: Id0b2b9e9ae2755ed89cee337a1a085fc4e95b073 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/intel/cannonlake_rvp/dsdt.asl5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl
index 712ea0524a..9f19cfb3ac 100644
--- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl
+++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl
@@ -28,6 +28,11 @@ DefinitionBlock(
#include <soc/intel/cannonlake/acpi/globalnvs.asl>
Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/cannonlake/acpi/northbridge.asl>
+ #include <soc/intel/cannonlake/acpi/southbridge.asl>
+ }
}
#if IS_ENABLED(CONFIG_CHROMEOS)