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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-03-06 16:32:18 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-03-09 13:09:48 +0100
commit8340666cb18322cbf39110b82d83bf02bfa8c856 (patch)
treeb971f81ec8d3482a708b51da6be0420f0b1a31f5 /src/mainboard
parent233f5b3b0ed27348b68fbaa453184d4fdb7fa0dc (diff)
downloadcoreboot-8340666cb18322cbf39110b82d83bf02bfa8c856.tar.xz
intel/jarrell: Apply ROMCC workaround
Taken from intel/xe7501devkit, maybe it had same symptoms once. The call to ich5_watchdog_on() has side-effect of exploding the requirements for ROMCC internal arrays at compile-time. The hard-coded limit in question is MAX_RHS in util/romcc.c, the default of 127 comes from the rhs field defined with 7 bits. Before this patch intel/jarrell builds were using upto MAX_RHS=102, while other ROMCC boards built even with MAX_RHS=10. This workaround brings intel/jarrell to the same level. Change-Id: I162d801f81d9196403d88636eb9cb291c950ded0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5348 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/intel/jarrell/romstage.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c
index c6f014c08b..bddb34afe6 100644
--- a/src/mainboard/intel/jarrell/romstage.c
+++ b/src/mainboard/intel/jarrell/romstage.c
@@ -102,4 +102,8 @@ static void main(unsigned long bist)
dump_pci_device(PCI_DEV(0, 0x00, 0));
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
+ /* NOTE: ROMCC dies with an internal compiler error if the
+ * following line is removed.
+ */
+ print_debug("SDRAM is up.\n");
}