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authorKyösti Mälkki <kyosti.malkki@gmail.com>2012-04-18 20:33:35 +0300
committerPatrick Georgi <patrick@georgi-clan.de>2012-04-21 09:37:04 +0200
commit97c064f0346874dcf02d4b2700a7e7c7913b24c9 (patch)
tree4b54f54c2b3ba29bd55df69563fd990c442f105b /src/mainboard
parenta8111cf980e01e9f8706024f06c05840b5fc8bcf (diff)
downloadcoreboot-97c064f0346874dcf02d4b2700a7e7c7913b24c9.tar.xz
Intel e7505: enable ECC scrubbing
It takes about 3 seconds to scrub 8GiB DDR266 RAM. After ECC scrub XIP cache is disabled for system stability. There is very little to do in romstage after ECC scrub, especially when RAM debug messages are turned off. So the delay caused by this is hardly noticeable. Cache for complete ROM is re-enabled before ramstage is decompressed, and it has no unstability issues. So the code required to re-enable cache for ROM currently already exists in cache-as-ram_ht.inc. A Kconfig option HW_SCRUBBER enables the scrub to be run on hard reboots and power-ons. Change-Id: Icf27acf73240c06b58091f1229efc0f01cca3f85 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/905 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/aopen/dxplplusu/Kconfig1
-rw-r--r--src/mainboard/aopen/dxplplusu/romstage.c19
2 files changed, 18 insertions, 2 deletions
diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig
index da03491d87..b6fbf45745 100644
--- a/src/mainboard/aopen/dxplplusu/Kconfig
+++ b/src/mainboard/aopen/dxplplusu/Kconfig
@@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select UDELAY_TSC
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_512
+ select HW_SCRUBBER
config MAINBOARD_DIR
string
diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c
index 73e445b7ce..ee900e9e12 100644
--- a/src/mainboard/aopen/dxplplusu/romstage.c
+++ b/src/mainboard/aopen/dxplplusu/romstage.c
@@ -68,8 +68,23 @@ void main(unsigned long bist)
// If this is a warm boot, some initialization can be skipped
if (!bios_reset_detected()) {
enable_smbus();
- sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
+
+ /* The real MCH initialisation. */
+ e7505_mch_init(memctrl);
+
+ /*
+ * ECC scrub invalidates cache, so all stack in CAR
+ * is lost. Only return addresses from main() and
+ * scrub_ecc() are recovered to stack via xmm0-xmm3.
+ */
+#if CONFIG_HW_SCRUBBER
+ unsigned long ret_addr = (unsigned long)((unsigned long*)&bist - 1);
+ e7505_mch_scrub_ecc(ret_addr);
+#endif
+
+ /* Hook for post ECC scrub settings and debug. */
+ e7505_mch_done(memctrl);
}
- print_debug("SDRAM is up.\n");
+ printk(BIOS_DEBUG, "SDRAM is up.\n");
}