summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
authorIvy Jian <ivy_jian@compal.corp-partner.google.com>2021-04-13 14:04:12 +0800
committerPatrick Georgi <pgeorgi@google.com>2021-04-16 06:45:32 +0000
commita7696adbeb1f3ad7408a02ba82930c02079b01ed (patch)
tree7ecd417ee3cb2a86e12d56fd2d3623b0b8360018 /src/mainboard
parenta0d48096ad83813d959886ba354f7b7eb0aea179 (diff)
downloadcoreboot-a7696adbeb1f3ad7408a02ba82930c02079b01ed.tar.xz
soc/amd/cezanne: Add uart controllers to chipset.cb
Add uart controller to chipset.cb and leave it off by default. Turn uart0 on for console for mainboards. BUG=none TEST=builds and boot into OS Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Iaeb7fea4b92bd89331c7ae7c1c000f8d9961fe9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/amd/majolica/devicetree.cb2
-rw-r--r--src/mainboard/google/guybrush/variants/baseboard/devicetree.cb3
-rw-r--r--src/mainboard/google/mancomb/variants/baseboard/devicetree.cb3
3 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/amd/majolica/devicetree.cb b/src/mainboard/amd/majolica/devicetree.cb
index 088b259261..fec764e0a5 100644
--- a/src/mainboard/amd/majolica/devicetree.cb
+++ b/src/mainboard/amd/majolica/devicetree.cb
@@ -75,4 +75,6 @@ chip soc/amd/cezanne
end
end
+ device ref uart_0 on end # UART0
+
end
diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
index 5e9037abe6..f044b8be7f 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
@@ -142,4 +142,7 @@ chip soc/amd/cezanne
device i2c 50 on end
end
end
+
+ device ref uart_0 on end # UART0
+
end # chip soc/amd/cezanne
diff --git a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb
index 0a604a37f5..9c1ba27b63 100644
--- a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb
@@ -130,4 +130,7 @@ chip soc/amd/cezanne
end
end
end # domain
+
+ device ref uart_0 on end # UART0
+
end # chip soc/amd/cezanne