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authorFurquan Shaikh <furquan@google.com>2019-07-06 22:09:28 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-07-07 07:51:24 +0000
commita913b3df90da925246936cb421afe01901172211 (patch)
treee31bcebc543bf13b61483c5cfbb9bce5ae11547b /src/mainboard
parentdb6c3f25f0d4b7fc0fd7aefb0b2442584a7f2c99 (diff)
downloadcoreboot-a913b3df90da925246936cb421afe01901172211.tar.xz
soc/intel/cannonlake: Use SA_DEV_ROOT instead of PCH_DEV_PMC
PMC device gets hidden from PCI bus after FSP-S call. Thus, it gets removed from the root bus as leftover unused device. With change 903b40a8a46 ("soc/intel: Replace uses of dev_find_slot()"), all uses of dev_find_slot() were replaced by pcidev_path_on_root() which relies on scanning of root bus to find the requested device. Since PMC device is removed from the root bus, pcidev_path_on_root() returns NULL for it thus resulting in configuration being skipped for the PMC ultimately resulting in S3 failures. Since the PCH_DEV_PMC was just used to get to chip config, this change replaces the use of PCH_DEV_PMC with SA_DEV_ROOT. BUG=b:136861224 TEST=Verified that S3 works fine on hatch. Change-Id: Ie5ade00ac2aca697608f1bdea9764b71c26e2112 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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