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authorVladimir Serbinenko <phcoder@gmail.com>2016-02-10 03:07:42 +0100
committerVladimir Serbinenko <phcoder@gmail.com>2016-02-12 19:10:04 +0100
commitb2ad8108abe1e91603938610e2fd7b333b944c8a (patch)
tree24dcaa87bd6886a33c24e02cc2a4ad1f83c49196 /src/mainboard
parentcf0e9021daad9705b7b5733ecfcf141c8a2b5f5f (diff)
downloadcoreboot-b2ad8108abe1e91603938610e2fd7b333b944c8a.tar.xz
link: Support native raminit
Change-Id: I95173c06d334a340fa2157511a1d69f38877b264 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13665 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/link/Kconfig4
-rw-r--r--src/mainboard/google/link/devicetree.cb2
-rw-r--r--src/mainboard/google/link/romstage.c39
3 files changed, 32 insertions, 13 deletions
diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig
index f1ce0ece35..9c7fb5ef40 100644
--- a/src/mainboard/google/link/Kconfig
+++ b/src/mainboard/google/link/Kconfig
@@ -16,10 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SERIRQ_CONTINUOUS_MODE
select MAINBOARD_HAS_NATIVE_VGA_INIT
-config USE_NATIVE_RAMINIT
- bool
- default n
-
config CHROMEOS
select CHROMEOS_VBNV_CMOS
select LID_SWITCH
diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb
index 5ac8d6b4b1..437b3cbfc8 100644
--- a/src/mainboard/google/link/devicetree.cb
+++ b/src/mainboard/google/link/devicetree.cb
@@ -18,6 +18,8 @@ chip northbridge/intel/sandybridge
register "gpu_cpu_backlight" = "0x00000200"
register "gpu_pch_backlight" = "0x04000000"
+ register "max_mem_clock_mhz" = "666"
+
device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989
device lapic 0 on end
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index 5710ccd96a..22b40a0f50 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -29,6 +29,7 @@
#include <console/console.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/gpio.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include "ec/google/chromeec/ec.h"
@@ -115,10 +116,10 @@ void rcba_config(void)
RCBA32(FD) = reg32;
}
-static void copy_spd(struct pei_data *peid)
+static uint8_t *locate_spd(void)
{
const int gpio_vector[] = {41, 42, 43, 10, -1};
- char *spd_file;
+ uint8_t *spd_file;
size_t spd_file_len;
int spd_index = get_gpios(gpio_vector);
@@ -128,18 +129,15 @@ static void copy_spd(struct pei_data *peid)
if (!spd_file)
die("SPD data not found.");
- if (spd_file_len < ((spd_index + 1) * sizeof(peid->spd_data[0]))) {
+ if (spd_file_len < ((spd_index + 1) * 256)) {
printk(BIOS_ERR, "spd index override to 0 - old hardware?\n");
spd_index = 0;
}
- if (spd_file_len < sizeof(peid->spd_data[0]))
+ if (spd_file_len < 256)
die("Missing SPD data.");
- memcpy(peid->spd_data[0],
- spd_file +
- spd_index * sizeof(peid->spd_data[0]),
- sizeof(peid->spd_data[0]));
+ return spd_file + spd_index * 256;
}
void mainboard_fill_pei_data(struct pei_data *pei_data)
@@ -190,7 +188,30 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
},
};
*pei_data = pei_data_template;
- copy_spd(pei_data);
+ memcpy(pei_data->spd_data[0], locate_spd(),
+ sizeof(pei_data->spd_data[0]));
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ /* enabled power usb oc pin */
+ { 0, 0, -1 }, /* P0: Empty */
+ { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */
+ { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */
+ { 1, 0, -1 }, /* P3: SDCARD (no OC) */
+ { 0, 0, -1 }, /* P4: Empty */
+ { 1, 0, -1 }, /* P5: WWAN (no OC) */
+ { 0, 0, -1 }, /* P6: Empty */
+ { 0, 0, -1 }, /* P7: Empty */
+ { 1, 0, -1 }, /* P8: Camera (no OC) */
+ { 1, 0, -1 }, /* P9: Bluetooth (no OC) */
+ { 0, 0, -1 }, /* P10: Empty */
+ { 0, 0, -1 }, /* P11: Empty */
+ { 0, 0, -1 }, /* P12: Empty */
+ { 0, 0, -1 }, /* P13: Empty */
+};
+
+void mainboard_get_spd(spd_raw_data *spd) {
+ memcpy(&spd[0], locate_spd(), 128);
}
void mainboard_early_init(int s3resume)