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authorSakari Ailus <sakari.ailus@linux.intel.com>2019-11-01 18:01:24 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-12-02 12:58:42 +0000
commitbe0dfef30c00dab0e4cb37f340f8424d8695f884 (patch)
tree300a4da38c0bd4b79e0c1d8789282e3ab88ad96e /src/mainboard
parentc0b9c8cbc014662dccdab98841a47dca2570dc0d (diff)
downloadcoreboot-be0dfef30c00dab0e4cb37f340f8424d8695f884.tar.xz
mb/google/poppy: Rework OV13858 power on sequence
In particular: - Set voltage before enabling regulators - Enable regulators and the clock without any sleeping in between. There's no need to wait there. - Sleep 1 ms in order to wait for regulator voltages settling before lifting xshutdown. BUG=chromium:959232 Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Tested-by: Jacopo Mondi <jacopo@jmondi.org> Change-Id: I0f8857ae369d5038f293a0e2c48c681df535ad86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl24
1 files changed, 17 insertions, 7 deletions
diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl
index 355b25528e..fc23d065b7 100644
--- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl
+++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl
@@ -468,23 +468,33 @@ Scope (\_SB.PCI0.I2C2)
C0GP = 1
}
- VACT = 1
if (LNotEqual (ACVA, 109)) {
/* Set ANA at 2.8152V */
ACVA = 109
}
- Sleep(3)
-
- \_SB.PCI0.I2C2.PMIC.CLKE()
- CLE0 = 1
+ VACT = 1
- VDCT = 1
if (LNotEqual (DCVA, 12)) {
/* Set CORE at 1.2V */
DCVA = 12
}
- Sleep(3)
+ VDCT = 1
+
+ \_SB.PCI0.I2C2.PMIC.CLKE()
+ CLE0 = 1
+
+ /*
+ * Wait for all regulator
+ * outputs to settle.
+ */
+ Sleep(1)
+
\_SB.PCI0.I2C2.PMIC.CRST(1)
+
+ /*
+ * 5 ms needed before
+ * streaming on.
+ */
Sleep(5)
STA = 1