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authorAndrey Petrov <andrey.petrov@intel.com>2016-08-25 11:06:08 -0700
committerAndrey Petrov <andrey.petrov@intel.com>2016-08-31 19:23:50 +0200
commitc42a9ac4abcf0710fa15e2e8cf3b1321bd9f3360 (patch)
tree7ceb28005be0e7738a80d91d455c8f214c63b843 /src/mainboard
parent07215aaf71cd617e9929ebfbba733954d6b0aa74 (diff)
downloadcoreboot-c42a9ac4abcf0710fa15e2e8cf3b1321bd9f3360.tar.xz
soc/intel/apollolake: Disable Periodic Retraining per-SKU
Certain LPDDR4 models have some HW issues that can be worked around by turning off Periodic Retraining feature in the memory controller. Add option to disable PR per SKU. BUG=chrome-os-partner:55466 TEST=run RMT test, pass Change-Id: Ie7aa79586665f6d3a7edd854a9eef07e6a1b2ab8 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/16320 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/reef/romstage.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c
index e8d8e1675e..964dee42cf 100644
--- a/src/mainboard/google/reef/romstage.c
+++ b/src/mainboard/google/reef/romstage.c
@@ -103,6 +103,7 @@ static const struct lpddr4_sku skus[] = {
.ch0_dual_rank = 1,
.ch1_dual_rank = 1,
.part_num = "MT53B512M32D2NP",
+ .disable_periodic_retraining = 1,
},
/* MT53B256M32D1NP-062 WT:C - both logical channels */
[3] = {
@@ -110,6 +111,7 @@ static const struct lpddr4_sku skus[] = {
.ch0_rank_density = LP4_8Gb_DENSITY,
.ch1_rank_density = LP4_8Gb_DENSITY,
.part_num = "MT53B256M32D1NP",
+ .disable_periodic_retraining = 1,
},
/* K4F8E304HB-MGCH - both logical channels */
[PROTO_SKU] = {