diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-12-09 17:43:27 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-12-18 20:52:01 +0100 |
| commit | c86c6b33e8ca32ffa0f0d7e30f35f1fb31fe3b4a (patch) | |
| tree | 12171a9fa9d44cc55363defd7a6388ca3a10a898 /src/mainboard | |
| parent | c3e0389c058ea097e80d6d95434b56b6edff8389 (diff) | |
| download | coreboot-c86c6b33e8ca32ffa0f0d7e30f35f1fb31fe3b4a.tar.xz | |
intel cache-as-ram: Move DCACHE_RAM_BASE
Having same memory region set as both WRPROT and WRBACK
using MTRRs is undefined behaviour. This could happen if
we allow DCACHE_RAM_BASE to be located within CBFS in SPI
flash memory and XIP romstage is at the same location.
As SPI master by default decodes all of top 16MiB below
4GiB, initial cache-as-ram line fills may have actually
read from SPI flash even in the case DCACHE_RAM_BASE was
below the nominal 4GiB - ROM_SIZE.
There are no reasons to have this as board-specific setting.
Change-Id: I2cce80731ede2e7f78197d9b0c77c7e9957a81b5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17806
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/apple/macbook21/Kconfig | 8 | ||||
| -rw-r--r-- | src/mainboard/asus/dsbf/Kconfig | 8 | ||||
| -rw-r--r-- | src/mainboard/ibase/mb899/Kconfig | 8 | ||||
| -rw-r--r-- | src/mainboard/lenovo/t60/Kconfig | 8 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x60/Kconfig | 8 | ||||
| -rw-r--r-- | src/mainboard/supermicro/x7db8/Kconfig | 8 |
6 files changed, 0 insertions, 48 deletions
diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig index ebf3954dac..4f51a28adf 100644 --- a/src/mainboard/apple/macbook21/Kconfig +++ b/src/mainboard/apple/macbook21/Kconfig @@ -27,14 +27,6 @@ config MAINBOARD_DIR string default apple/macbook21 -config DCACHE_RAM_BASE - hex - default 0xffdf8000 - -config DCACHE_RAM_SIZE - hex - default 0x8000 - if BOARD_APPLE_MACBOOK21 config MAINBOARD_PART_NUMBER diff --git a/src/mainboard/asus/dsbf/Kconfig b/src/mainboard/asus/dsbf/Kconfig index 481d4fa1d8..fa0b659e74 100644 --- a/src/mainboard/asus/dsbf/Kconfig +++ b/src/mainboard/asus/dsbf/Kconfig @@ -15,14 +15,6 @@ config MAINBOARD_DIR string default asus/dsbf -config DCACHE_RAM_BASE - hex - default 0xffdf8000 - -config DCACHE_RAM_SIZE - hex - default 0x8000 - config MAINBOARD_PART_NUMBER string default "DSBF" diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig index 4f646acb35..3208a93ee9 100644 --- a/src/mainboard/ibase/mb899/Kconfig +++ b/src/mainboard/ibase/mb899/Kconfig @@ -21,14 +21,6 @@ config MAINBOARD_DIR string default ibase/mb899 -config DCACHE_RAM_BASE - hex - default 0xffdf8000 - -config DCACHE_RAM_SIZE - hex - default 0x8000 - config MAINBOARD_PART_NUMBER string default "MB899" diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index 8e1ee1e70b..9fb46e2eb6 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -30,14 +30,6 @@ config MAINBOARD_DIR string default lenovo/t60 -config DCACHE_RAM_BASE - hex - default 0xffdf8000 - -config DCACHE_RAM_SIZE - hex - default 0x8000 - config MAINBOARD_PART_NUMBER string default "ThinkPad T60" diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index eecaf6407e..d80b22d34d 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -33,14 +33,6 @@ config MAINBOARD_DIR string default lenovo/x60 -config DCACHE_RAM_BASE - hex - default 0xffdf8000 - -config DCACHE_RAM_SIZE - hex - default 0x8000 - config MAINBOARD_PART_NUMBER string default "ThinkPad X60" diff --git a/src/mainboard/supermicro/x7db8/Kconfig b/src/mainboard/supermicro/x7db8/Kconfig index 82a4ebb27e..fd71254cb1 100644 --- a/src/mainboard/supermicro/x7db8/Kconfig +++ b/src/mainboard/supermicro/x7db8/Kconfig @@ -15,14 +15,6 @@ config MAINBOARD_DIR string default supermicro/x7db8 -config DCACHE_RAM_BASE - hex - default 0xffdf8000 - -config DCACHE_RAM_SIZE - hex - default 0x8000 - config MAINBOARD_PART_NUMBER string default "X7DB8 / X7DB8+" |