diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-03-01 02:12:58 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-02 11:51:23 +0000 |
| commit | cfe1016883b711e0a76d3dcbc9151813d648619b (patch) | |
| tree | ab82c33c796b5717d81d50dea3d3b856ead50f5f /src/mainboard | |
| parent | 59e7a43f9a3bfad60d2ae0078b65deca8d468381 (diff) | |
| download | coreboot-cfe1016883b711e0a76d3dcbc9151813d648619b.tar.xz | |
mb/**/dsdt.asl: Remove outdated sleepstates.asl comment
Previously, each Intel chipset had its own sleepstates.asl file.
However, this is no longer the case, so drop these comments.
This follows commit 408d1dac9e23250c0e485bbf934771f769b717c1.
Change-Id: I0c0f4ad8bf743010ebdd2d53fcf297aeab64a662
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/dedede/dsdt.asl | 1 | ||||
| -rw-r--r-- | src/mainboard/google/volteer/dsdt.asl | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/jasperlake_rvp/dsdt.asl | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/tglrvp/dsdt.asl | 1 |
4 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl index 4134b036da..45a1486b55 100644 --- a/src/mainboard/google/dedede/dsdt.asl +++ b/src/mainboard/google/dedede/dsdt.asl @@ -38,7 +38,6 @@ DefinitionBlock( /* Chrome OS specific */ #include <vendorcode/google/chromeos/acpi/chromeos.asl> - /* Chipset specific sleep states */ #include <southbridge/intel/common/acpi/sleepstates.asl> /* Chrome OS Embedded Controller */ diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index e4bbe90d70..f62780bccc 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -47,6 +47,5 @@ DefinitionBlock( #include <ec/google/chromeec/acpi/ec.asl> } - // Chipset specific sleep states #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/jasperlake_rvp/dsdt.asl b/src/mainboard/intel/jasperlake_rvp/dsdt.asl index 8788a1f71d..4b9a696214 100644 --- a/src/mainboard/intel/jasperlake_rvp/dsdt.asl +++ b/src/mainboard/intel/jasperlake_rvp/dsdt.asl @@ -58,7 +58,6 @@ DefinitionBlock( } #endif - /* Chipset specific sleep states */ #include <southbridge/intel/common/acpi/sleepstates.asl> /* Mainboard specific */ diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl index a17f597e6b..8236ccb110 100644 --- a/src/mainboard/intel/tglrvp/dsdt.asl +++ b/src/mainboard/intel/tglrvp/dsdt.asl @@ -58,7 +58,6 @@ DefinitionBlock( } #endif - /* Chipset specific sleep states */ #include <southbridge/intel/common/acpi/sleepstates.asl> /* Mainboard specific */ |