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authorRonak Kanabar <ronak.kanabar@intel.com>2019-01-09 15:50:12 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-01-17 13:04:35 +0000
commitd266710d2cca38f417e96447d76b9bfd3fda18f1 (patch)
treeba5e0e019ac10ba3ae9cf3ca9507209d5d0c7475 /src/mainboard
parentdc666f50c7bd479caf9d9b91a1769686c15cfdf9 (diff)
downloadcoreboot-d266710d2cca38f417e96447d76b9bfd3fda18f1.tar.xz
mb/google/hatch: Configure miscellaneous features
set SaGv = SaGv_Enabled , To Enable System Agent dynamic frequency support set HeciEnabled = 1, To Enable heci communication set speed_shift_enable = 1 To Enable Speed Shift Technology support Change-Id: Iea90a65a77ef5e45a802cfe6fd31e1921163b02b Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/30774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/hatch/variants/baseboard/devicetree.cb6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 8dd2d849be..5b777f840d 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -48,6 +48,12 @@ chip soc/intel/cannonlake
register "SataPortsEnable[1]" = "1"
register "SataPortsDevSlp[1]" = "1"
register "satapwroptimize" = "1"
+ # Enable System Agent dynamic frequency
+ register "SaGv" = "SaGv_Enabled"
+ # Enable heci communication
+ register "HeciEnabled" = "1"
+ # Enable Speed Shift Technology support
+ register "speed_shift_enable" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1