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authorLijian Zhao <lijian.zhao@intel.com>2019-01-11 11:54:09 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-01-16 13:39:39 +0000
commitd4a12ec82204b9acf8dc814103e4f2efefecd248 (patch)
tree7aaa9c7c6d162d4ae02c2725ebb656ea5dbf2d7f /src/mainboard
parent37d4ffb0a56bc127111c9f10ffe31e3a55e133ee (diff)
downloadcoreboot-d4a12ec82204b9acf8dc814103e4f2efefecd248.tar.xz
mb/google/sarien: Enable Camarillo Device
Whiskeylake processor have an internal device called Camarillo dedicated for thermal management support, turn it on so processor thermal driver can be loaded. BUG=N/A TEST=Boot up and run lspci on Sarien board, Bus 0 Device 4 Funcion 0 can be seen. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I937960fde2704cddb1fe0058ab622f4b5de401d7 Reviewed-on: https://review.coreboot.org/c/30858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/sarien/variants/arcada/devicetree.cb1
-rw-r--r--src/mainboard/google/sarien/variants/sarien/devicetree.cb1
2 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index fa926aea09..ff26cbf49f 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -35,6 +35,7 @@ chip soc/intel/cannonlake
register "satapwroptimize" = "1"
register "tdp_pl1_override" = "25"
register "tdp_pl2_override" = "51"
+ register "Device4Enable" = "1"
# Intel Common SoC Config
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 48404a8b64..37ef3dc5e0 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -44,6 +44,7 @@ chip soc/intel/cannonlake
register "SlowSlewRateForFivr" = "2"
register "tdp_pl1_override" = "25"
register "tdp_pl2_override" = "51"
+ register "Device4Enable" = "1"
# Intel Common SoC Config
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port