diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-02-08 16:58:47 -0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-02-16 04:35:43 +0000 |
| commit | e1b8221498b6742cd87271d736ffc6f8f0f82633 (patch) | |
| tree | 1b3b00c8c8acdb5e298dcdc8c303f9faaa21bdce /src/mainboard | |
| parent | 20123a8838e5c8cdf002237dcf68aa048dc2161b (diff) | |
| download | coreboot-e1b8221498b6742cd87271d736ffc6f8f0f82633.tar.xz | |
soc/intel/cannonlake: Update GPIO ASL
GPIO pin definition had been updated to match Cannonlake PCH-LP EDS,
hence the ACPI dsdt table will include those changes as well.
BUG=None
TEST=Build coreboot image, flah coreboot image into DUT, and target
system can boot up into OS.
Change-Id: I958e0cb71b4e656bec9bfe2d12076b577b57629b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard')
0 files changed, 0 insertions, 0 deletions