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authorWisley Chen <wisley.chen@quantatw.com>2017-03-06 07:00:57 -0500
committerMartin Roth <martinroth@google.com>2017-03-08 04:37:30 +0100
commite4c85c128a5056e3f1ca7692edec97b33437da13 (patch)
tree7af2861f19febc75f99353a54eaf1f2a754efa31 /src/mainboard
parent8c247a2a796f158664d3f1bba130c48bf4e1497c (diff)
downloadcoreboot-e4c85c128a5056e3f1ca7692edec97b33437da13.tar.xz
mainboard/google/snappy: Override USB2 phy setting
Fine tune USB2, need to override the following registers. port#1: PERPORTPETXISET=7 PERPORTTXISET=0 BUG=b:35858164 BRANCH=reef TEST=built, measured eye diagram on snappy, and reviewed by intel Change-Id: I461cf8f032b4e70abc9707e6cd3603a62cee448f Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18590 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/reef/variants/snappy/devicetree.cb6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb
index 6d1c9ef145..2b47c5727d 100644
--- a/src/mainboard/google/reef/variants/snappy/devicetree.cb
+++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb
@@ -112,6 +112,12 @@ chip soc/intel/apollolake
# Minimum SLP S3 assertion width 28ms.
register "slp_s3_assertion_width_usecs" = "28000"
+ # Override USB2 PER PORT register (PORT 1)
+ register "usb2eye[1]" = "{
+ .Usb20PerPortPeTxiSet = 7,
+ .Usb20PerPortTxiSet = 0,
+ }"
+
device domain 0 on
device pci 00.0 on end # - Host Bridge
device pci 00.1 on end # - DPTF