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authorKarthikeyan Ramasubramanian <kramasub@google.com>2020-01-06 22:21:37 -0700
committerFurquan Shaikh <furquan@google.com>2020-01-27 04:47:39 +0000
commitedad34b883efc20c9cd28b96ec77318556508663 (patch)
treee264bcf3d67af3477152467580215a18dff5af03 /src/mainboard
parent85c52c5d97070b2e07d34e3a6c60ef5609b8bf2d (diff)
downloadcoreboot-edad34b883efc20c9cd28b96ec77318556508663.tar.xz
mb/google/dedede: Enable ACPI and add ACPI table
Enable ACPI configuration and add DSDT ACPI table. BUG=b:144768001 TEST=Build Test Change-Id: I0aa889cd52bff3e1e9ff7b7b93ec1000045bcfd2 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/dedede/Kconfig2
-rw-r--r--src/mainboard/google/dedede/dsdt.asl41
-rw-r--r--src/mainboard/google/dedede/mainboard.c10
3 files changed, 52 insertions, 1 deletions
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig
index 7c42404d09..21ba001757 100644
--- a/src/mainboard/google/dedede/Kconfig
+++ b/src/mainboard/google/dedede/Kconfig
@@ -1,5 +1,7 @@
config BOARD_GOOGLE_BASEBOARD_DEDEDE
def_bool n
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
select SOC_INTEL_JASPERLAKE
if BOARD_GOOGLE_BASEBOARD_DEDEDE
diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl
new file mode 100644
index 0000000000..c387fd38d7
--- /dev/null
+++ b/src/mainboard/google/dedede/dsdt.asl
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2020 The coreboot project Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <arch/acpi.h>
+#include <variant/gpio.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, /* DSDT revision: ACPI v2.0 and up */
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725 /* OEM revision */
+)
+{
+ /* Some generic macros */
+ #include <soc/intel/tigerlake/acpi/platform.asl>
+
+ /* global NVS and variables */
+ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+ /* CPU */
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+ #include <soc/intel/tigerlake/acpi/southbridge.asl>
+ }
+ }
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+}
diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c
index 3b36abe661..b663a43071 100644
--- a/src/mainboard/google/dedede/mainboard.c
+++ b/src/mainboard/google/dedede/mainboard.c
@@ -6,6 +6,7 @@
* SPDX-License-Identifier: GPL-2.0-or-later
*/
+#include <arch/acpi.h>
#include <baseboard/variants.h>
#include <device/device.h>
@@ -18,9 +19,16 @@ static void mainboard_init(void *chip_info)
gpio_configure_pads(pads, num);
}
+static unsigned long mainboard_write_acpi_tables(
+ struct device *device, unsigned long current, acpi_rsdp_t *rsdp)
+{
+ return current;
+}
+
static void mainboard_enable(struct device *dev)
{
- /* TODO: Enable mainboard */
+ dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
+ dev->ops->acpi_inject_dsdt_generator = NULL;
}
struct chip_operations mainboard_ops = {