armv7: add new dcache and MMU setup functions

This adds new MMU setup code. Most notably, this version uses
cbmem_add() to determine the translation table base address, which
in turn is necessary to ensure payloads which wipe memory can tell
which regions to wipe out.

TODOs:
- Finish cleaning up references to old cache/MMU stuff
- Add L2 setup (from exynos_cache.c)
- Set up ranges dynamically rather than in ramstage's main().

Change-Id: Iba5295a801e8058a3694e4ec5b94bbe9a69d3ee6
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2877
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

2 files changed, 23 insertions, 8 deletions

diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c
index be5216f2b7..1751a1b8aa 100644
--- a/src/mainboard/google/snow/ramstage.c
+++ b/src/mainboard/google/snow/ramstage.c
@@ -23,19 +23,37 @@
 #include <cpu/samsung/exynos5250/clk.h>
 #include <cpu/samsung/exynos5250/power.h>
 
+#include <arch/cache.h>
+
+/* convenient shorthand (in MB) */
+#define DRAM_START	(CONFIG_SYS_SDRAM_BASE >> 20)
+#define DRAM_SIZE	CONFIG_DRAM_SIZE_MB
+#define DRAM_END	(DRAM_START + DRAM_SIZE)	/* plus one... */
+
 void hardwaremain(int boot_complete);
 void main(void)
 {
 	console_init();
 	printk(BIOS_INFO, "hello from ramstage; now with deluxe exception handling.\n");
 
-	/* this is going to move, but we must have it now and we're not sure where */
-	exception_init();
-	/* place at top of physical memory */
+	/* set up coreboot tables */
 	high_tables_size = CONFIG_COREBOOT_TABLES_SIZE;
 	high_tables_base = CONFIG_SYS_SDRAM_BASE +
-			((CONFIG_DRAM_SIZE_MB << 20UL) * CONFIG_NR_DRAM_BANKS) -
-			CONFIG_COREBOOT_TABLES_SIZE;
+				((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) -
+				CONFIG_COREBOOT_TABLES_SIZE;
+	cbmem_init(high_tables_base, high_tables_size);
+
+	/* set up dcache and MMU */
+	/* FIXME: this should happen via resource allocator */
+	mmu_init();
+	mmu_config_range(0, DRAM_START, DCACHE_OFF);
+	mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
+	mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
+	dcache_invalidate_all();
+	dcache_mmu_enable();
+
+	/* this is going to move, but we must have it now and we're not sure where */
+	exception_init();
 
 	const unsigned epll_hz = 192000000;
 	const unsigned sample_rate = 48000;
diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c
index bfb4156b68..39069b2d95 100644
--- a/src/mainboard/google/snow/romstage.c
+++ b/src/mainboard/google/snow/romstage.c
@@ -113,9 +113,6 @@ void main(void)
 		while(1);
 	}
 
-	/* Set up MMU and caches */
-	mmu_setup_by_mva(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB);
-
 	initialize_s5p_mshc();
 
 	graphics();