diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2017-12-07 17:01:46 -0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-12-12 05:17:45 +0000 |
| commit | 060e2eb4f0e1c0de2afebcd9531734081f655897 (patch) | |
| tree | 06b217b5b80822f6145cd9c08f0e7430dbe6a35e /src/mainboard | |
| parent | d46e216d003b706ad5cbaa922b5faf3d1513a0e6 (diff) | |
| download | coreboot-060e2eb4f0e1c0de2afebcd9531734081f655897.tar.xz | |
mb/google/poppy/variants/nami: Implement variant_memory_params
This change provides implementation of variant_memory_params for
nami. Since it uses DDR4 memory, DQ-DQS mapping table is not
required. Also, Rcomp resistor values are provided based on SDP v/s
DDP memory.
BUG=b:70188937
Change-Id: Ic1d0cfdb7d8b02fa0be0a4c54b20057a4c2fc3ce
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/poppy/variants/nami/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/mainboard/google/poppy/variants/nami/memory.c | 48 |
2 files changed, 52 insertions, 0 deletions
diff --git a/src/mainboard/google/poppy/variants/nami/Makefile.inc b/src/mainboard/google/poppy/variants/nami/Makefile.inc index 0050a3b3bd..06f98017ca 100644 --- a/src/mainboard/google/poppy/variants/nami/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nami/Makefile.inc @@ -1,7 +1,11 @@ +# IMPORTANT!! When a new memory SPD is added here, please ensure that ddp_bitmap +# is correctly updated in memory.c to indicate if memory id is using DDP. SPD_SOURCES = empty # 0b0000 bootblock-y += gpio.c +romstage-y += memory.c + ramstage-y += gpio.c ramstage-y += pl2.c diff --git a/src/mainboard/google/poppy/variants/nami/memory.c b/src/mainboard/google/poppy/variants/nami/memory.c new file mode 100644 index 0000000000..dec7626b73 --- /dev/null +++ b/src/mainboard/google/poppy/variants/nami/memory.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <string.h> + +/* Rcomp resistor */ +static const u16 rcomp_resistor_ddp[] = { 121, 81, 100 }; +static const u16 rcomp_resistor_sdp[] = { 200, 81, 100 }; + +/* Rcomp target */ +static const u16 rcomp_target[] = { 100, 40, 20, 20, 26 }; + +/* Memory ids are 1-indexed, so subtract 1 to use 0-indexed values in bitmap. */ +#define MEM_ID(x) (1 << ((x) - 1)) + +/* Bitmap to indicate which memory ids are using DDP. */ +static const uint16_t ddp_bitmap = MEM_ID(4); + +void variant_memory_params(struct memory_params *p) +{ + memset(p, 0, sizeof(*p)); + p->type = MEMORY_DDR4; + + /* Rcomp resistor values are different for SDP and DDP. */ + if (ddp_bitmap & MEM_ID(variant_memory_sku())) { + p->rcomp_resistor = rcomp_resistor_ddp; + p->rcomp_resistor_size = sizeof(rcomp_resistor_ddp); + } else { + p->rcomp_resistor = rcomp_resistor_sdp; + p->rcomp_resistor_size = sizeof(rcomp_resistor_sdp); + } + + p->rcomp_target = rcomp_target; + p->rcomp_target_size = sizeof(rcomp_target); +} |