diff options
| author | Shaunak Saha <shaunak.saha@intel.com> | 2016-07-06 15:50:48 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-12 20:39:37 +0200 |
| commit | 066e0f392378fbb7e1628af937e88f86e1279158 (patch) | |
| tree | f2bb3649450f36100863b43cdcf7713fe09651f1 /src/mainboard | |
| parent | 6e5c5a15bc9fe709943598ede0eb52f9766cbb02 (diff) | |
| download | coreboot-066e0f392378fbb7e1628af937e88f86e1279158.tar.xz | |
google/reef: Add GPE routing settings
This patch sets the devicetree for gpe0_dw configuration
and also configures the GPIO lines for SCI. EC_SCI_GPI
is configured to proper value.
BUG = chrome-os-partner:53438
TEST = Toggle pch_sci_l from ec console using gpioset command
and see that the sci counter increases in /sys/firmware/acpi/interrupt
and also 9 in /proc/interrupt
Change-Id: If258bece12768edb1e612c982514ce95c756c438
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15556
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/reef/devicetree.cb | 9 | ||||
| -rw-r--r-- | src/mainboard/google/reef/ec.h | 8 | ||||
| -rw-r--r-- | src/mainboard/google/reef/gpio.h | 2 |
3 files changed, 15 insertions, 4 deletions
diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb index 33fa46e967..98e413b7d2 100644 --- a/src/mainboard/google/reef/devicetree.cb +++ b/src/mainboard/google/reef/devicetree.cb @@ -36,6 +36,15 @@ chip soc/intel/apollolake # 0x1C[6:0] stands for 28*125 = 3500 pSec delay for HS200 register "emmc_rx_cmd_data_cntl2" = "0x1001C" + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., if this route changes then the affected GPE + # offset bits also need to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_N_31_0" + register "gpe0_dw2" = "PMC_GPE_N_63_32" + register "gpe0_dw3" = "PMC_GPE_SW_31_0" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF diff --git a/src/mainboard/google/reef/ec.h b/src/mainboard/google/reef/ec.h index 5a32697d2e..3619c04229 100644 --- a/src/mainboard/google/reef/ec.h +++ b/src/mainboard/google/reef/ec.h @@ -18,9 +18,11 @@ #include <ec/google/chromeec/ec_commands.h> -/* This is the GPE status bit. - TODO: Fix this to proper bit matching GPE routing table */ -#define EC_SCI_GPI 15 +/* + * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0 + * which is North community + */ +#define EC_SCI_GPI GPE0_DW1_11 #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index cbad4c6b58..82a6a41a0f 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -282,7 +282,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_APIC(GPIO_9, NONE, DEEP, LEVEL, NONE), /* dTPM IRQ */ PAD_CFG_GPI(GPIO_10, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI_SCI(GPIO_11, NONE, DEEP, LEVEL, NONE), /* EC SCI */ + PAD_CFG_GPI_SCI(GPIO_11, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC SCI */ PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_13, UP_20K, DEEP), /* unused */ PAD_CFG_GPI_APIC(GPIO_14, UP_20K, DEEP, LEVEL, NONE), /* FP IRQ */ |