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authorMichael Niewöhner <foss@mniewoehner.de>2020-12-21 03:46:58 +0100
committerMichael Niewöhner <foss@mniewoehner.de>2021-01-21 19:01:58 +0000
commit18d360a5820ca208524886e96a35c5f296011fe2 (patch)
treec0b9cb5e67e23fd371e1488e49621c6044918746 /src/mainboard
parentf6d320060d4ab96fbe383cb9fd01fa43a8e022b7 (diff)
downloadcoreboot-18d360a5820ca208524886e96a35c5f296011fe2.tar.xz
mb/intel/kblrvp: do UART pad configuration at board-level
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to the early gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Also switch to `bootblock_mainboard_early_init` to configure the pads in early bootblock before console initialization, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: I8b30eb5d70c34ae3e2ed24ab52dd1357a54c5ae7 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49439 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/intel/kblrvp/bootblock.c2
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h2
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h2
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h2
4 files changed, 7 insertions, 1 deletions
diff --git a/src/mainboard/intel/kblrvp/bootblock.c b/src/mainboard/intel/kblrvp/bootblock.c
index 19c5e9efb8..41105826fb 100644
--- a/src/mainboard/intel/kblrvp/bootblock.c
+++ b/src/mainboard/intel/kblrvp/bootblock.c
@@ -12,7 +12,7 @@ static void early_config_gpio(void)
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}
-void bootblock_mainboard_init(void)
+void bootblock_mainboard_early_init(void)
{
early_config_gpio();
}
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h
index 4f7f002bff..354a4ff157 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h
+++ b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h
@@ -267,6 +267,8 @@ static const struct pad_config gpio_table[] = {
static const struct pad_config early_gpio_table[] = {
/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
+/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
};
#endif
diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h
index ff4647f1d2..a60850545f 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h
+++ b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h
@@ -197,6 +197,8 @@ static const struct pad_config gpio_table[] = {
static const struct pad_config early_gpio_table[] = {
/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
+/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
};
#endif
diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h
index 37193cfcda..5b588a10c3 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h
+++ b/src/mainboard/intel/kblrvp/variants/rvp8/include/variant/gpio.h
@@ -163,6 +163,8 @@ static const struct pad_config gpio_table[] = {
static const struct pad_config early_gpio_table[] = {
/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
+/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
};
#endif