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| author | Duncan Laurie <dlaurie@chromium.org> | 2017-05-03 10:14:07 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2017-05-04 01:57:46 +0200 |
| commit | 1a51086815c099127ec4253e9785b664f2c933f4 (patch) | |
| tree | 13db17739966d37862d81f397d3dcdb06edb4961 /src/mainboard | |
| parent | fff2e6c5561889aaf0dec3b8c94f642aec8701ed (diff) | |
| download | coreboot-1a51086815c099127ec4253e9785b664f2c933f4.tar.xz | |
mb/google/eve: Set SUSWARN# pin to native function
Set GPP_A13/SUSWARN# pin mode to native function 1. This pin is tied
to SUSACK# in the schematic and and is intented to be used in Deep Sx
so it should not be configured for GPIO mode.
BUG=b:35581264
TEST=build and boot on Eve platform, test that Deep S3 and Deep S5
are still functional. (this change should have no visible effect)
Change-Id: Ie2dc24d095872ab93a5bfcbe5307c3b7a8e4dbcc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/eve/gpio.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h index 6da82441bd..ed0d7126a0 100644 --- a/src/mainboard/google/eve/gpio.h +++ b/src/mainboard/google/eve/gpio.h @@ -58,7 +58,7 @@ static const struct pad_config gpio_table[] = { /* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* PME# */ PAD_CFG_NC(GPP_A11), /* TP67 */ /* BM_BUSY# */ PAD_CFG_NC(GPP_A12), -/* SUSWARN# */ PAD_CFG_NC(GPP_A13), +/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* ESPI_RESET# */ /* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), |