diff options
| author | Ionela Voinescu <ionela.voinescu@imgtec.com> | 2015-03-05 13:09:57 +0000 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-21 08:23:37 +0200 |
| commit | 38063b050d73326409df06ea2620000720e24579 (patch) | |
| tree | 7aeb93791d9e10c852b0315c7bf75112fc6d855e /src/mainboard | |
| parent | 9ff8f6f818d4e5a8aa0fe21cbfaba9ccd865bc7b (diff) | |
| download | coreboot-38063b050d73326409df06ea2620000720e24579.tar.xz | |
pistachio: add clock setup for all I2C interfaces
BUG=chrome-os-partner:31438
TEST=tested on Pistachio bring up board; all I2C interfaces
were tested with the TPM and they all work properly.
BRANCH=none
Change-Id: I02202585140beb818212c02800f6b7e4966a922a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 33b2adecc4939ac73fffba47adf1c8306a888b8d
Original-Change-Id: Ida7eaa72d4d6e6b034319086410de5baa63788bc
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/256361
Original-Reviewed-by: Chris Lane <chris.lane@frontier-silicon.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9839
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/urara/bootblock.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/urara/bootblock.c b/src/mainboard/google/urara/bootblock.c index 814eb53631..c8e15c8899 100644 --- a/src/mainboard/google/urara/bootblock.c +++ b/src/mainboard/google/urara/bootblock.c @@ -193,7 +193,7 @@ static int init_clocks(void) uart1_clk_setup(6, 61); /* System PLL divided by 4 divided by 3 -> 33.33 MHz */ - i2c0_clk_setup(3, 2); + i2c_clk_setup(3, 2, 0); /* Ethernet clocks setup: ENET as clock source */ eth_clk_setup(0, 7); |